Hi Everyone,
Please find attached a patch to improve support to STM32F030.
BR,
Alan
From 28b5eec93eacc2ca110ca36b0074ac84f09c2574 Mon Sep 17 00:00:00 2001
From: Alan Carvalho de Assis <engenhari...@siam.ind.br>
Date: Wed, 5 Feb 2020 15:12:25 -0300
Subject: [PATCH] Add MemoryMap and PinMap support to STM32F030RC
---
arch/arm/include/stm32f0l0g0/chip.h | 21 +-
.../stm32f0l0g0/hardware/stm32_memorymap.h | 4 +-
.../src/stm32f0l0g0/hardware/stm32_pinmap.h | 4 +-
.../hardware/stm32f03x_memorymap.h | 152 +++++++++++
.../stm32f0l0g0/hardware/stm32f03x_pinmap.h | 256 ++++++++++++++++++
5 files changed, 434 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
create mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h
index 72336a2916..287ebb1fe4 100644
--- a/arch/arm/include/stm32f0l0g0/chip.h
+++ b/arch/arm/include/stm32f0l0g0/chip.h
@@ -50,7 +50,26 @@
/* Get customizations for each supported chip */
-#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
+#if defined(CONFIG_ARCH_CHIP_STM32F030RC)
+
+# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
+# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
+
+# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
+# define STM32_NI2S 0 /* No I2S modules */
+# define STM32_NI2C 2 /* Two I2C modules */
+# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
+# define STM32_NUSART 6 /* Six USARTs modules */
+# define STM32_NCAN 0 /* No CAN controllers */
+# define STM32_NUSBDEV 0 /* One USB full-speed device controller */
+# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
+# define STM32_NADC 1 /* One 12-bit module */
+# define STM32_NDAC 0 /* One DAC channel */
+# define STM32_NCOMP 0 /* Two Analog Comparators */
+# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */
+# define STM32_NPORTS 5 /* Six GPIO ports, GPIOA-F */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
# define STM32_SRAM_SIZE (8*1024) /* 8Kb */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
index ca15936ce2..d389de798b 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
@@ -44,7 +44,9 @@
#include <nuttx/config.h>
#include "chip.h"
-#if defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \
+#if defined(CONFIG_STM32F0L0G0_STM32F03X)
+# include "hardware/stm32f03x_memorymap.h"
+#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \
defined(CONFIG_STM32F0L0G0_STM32F09X)
# include "hardware/stm32f05xf07xf09x_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
index 63270d7cbb..86aaeecb60 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
@@ -43,7 +43,9 @@
#include <nuttx/config.h>
#include "chip.h"
-#if defined(CONFIG_STM32F0L0G0_STM32F05X)
+#if defined(CONFIG_STM32F0L0G0_STM32F03X)
+# include "hardware/stm32f03x_pinmap.h"
+#elif defined(CONFIG_STM32F0L0G0_STM32F05X)
# include "hardware/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0L0G0_STM32F07X)
# include "hardware/stm32f07x_pinmap.h"
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
new file mode 100644
index 0000000000..8a4ce2b0ae
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
@@ -0,0 +1,152 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
+ *
+ * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ * Alan Carvalho de Assis <acas...@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* ST32F05XF07X Address Blocks ******************************************************/
+
+#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+ /* 0x60000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK 0xf0000000
+#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses **************************************************************/
+
+#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
+ /* 0x00100000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
+ /* 0x08100000-0x0fffffff: Reserved */
+#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
+ /* 0x10010000-0x1ffeffff: Reserved */
+#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */
+ /* 0x1fff7a10-0x1fff7fff: Reserved */
+#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
+ /* 0x1fffc008-0x1fffffff: Reserved */
+
+/* System Memory Addresses **********************************************************/
+
+#define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */
+#define STM32_SYSMEM_FSIZE 0x1ffff7cc /* This bitfield indicates the size of
+ * the device Flash memory expressed in
+ * Kbytes. Example: 0x040 corresponds
+ * to 64 Kbytes
+ */
+
+/* Peripheral Base Addresses ********************************************************/
+
+#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
+ /* 0x4000a000-0x4000ffff: Reserved */
+#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */
+ /* 0x40016c00-0x4001ffff: Reserved */
+#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
+ /* 0x40024400-0x4007ffff: Reserved */
+#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */
+ /* 0x48001800-0x4fffFfff: Reserved */
+#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
+
+/* APB1 Base Addresses **************************************************************/
+
+ /* 0x40000000-0x400003ff Reserved */
+#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
+#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
+#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
+#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
+#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
+#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
+#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
+#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
+#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
+#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
+#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
+#define STM32_USART5_BASE 0x40005000 /* 0x40005000-0x400053ff USART5 */
+#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
+#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
+ /* 0x40005c00-0x40005fff Reserved */
+#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
+ /* 0x40007400-0x400077ff Reserved */
+
+/* APB2 Base Addresses **************************************************************/
+
+#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG + COMP + OPAMP */
+#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107ff EXTI */
+#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */
+#define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */
+#define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */
+#define STM32_ADC12_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 12 */
+#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
+#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
+#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
+#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
+#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
+#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
+#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
+
+/* AHB1 Base Addresses **************************************************************/
+
+#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
+ /* 0x40020400-0x400207ff: Reserved */
+#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */
+#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
+ /* 0x40024000-0x400243ff: Reserved */
+
+/* AHB2 Base Addresses **************************************************************/
+
+#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
+#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
+#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
+#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
+ /* 0x48001000-0x480013ff: Reserved */
+#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
+
+/* Cortex-M4 Base Addresses *********************************************************/
+/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
+ * address range
+ */
+
+#define STM32_SCS_BASE 0xe000e000
+#define STM32_DEBUGMCU_BASE 0xe0042000
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F03X_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
new file mode 100644
index 0000000000..598a2f850e
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
@@ -0,0 +1,256 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h
+ *
+ * Copyright (C) 2020 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ * Alan Carvalho de Assis <acas...@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Alternate Pin Functions.
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
+ * Drivers, however, will use the pin selection without the numeric suffix.
+ * Additional definitions are required in the board.h file. For example, if
+ * CAN1_RX connects vis PD0 on some board, then the following definition should
+ * appear inthe board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PD0 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as frequency,
+ * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
+ * pins in this file.
+ */
+
+/* ADC 1 */
+
+#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
+#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
+#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
+#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
+
+/* Events */
+
+#define GPIO_EVENTOUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_EVENTOUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_EVENTOUT_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_EVENTOUT_4 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_EVENTOUT_5 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_EVENTOUT_6 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN0)
+#define GPIO_EVENTOUT_7 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN1)
+#define GPIO_EVENTOUT_8 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN2)
+#define GPIO_EVENTOUT_9 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_EVENTOUT_10 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN4)
+#define GPIO_EVENTOUT_11 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN4)
+#define GPIO_EVENTOUT_12 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN5)
+#define GPIO_EVENTOUT_13 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_EVENTOUT_14 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_EVENTOUT_15 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_EVENTOUT_16 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_EVENTOUT_17 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_EVENTOUT_18 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_EVENTOUT_19 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_EVENTOUT_20 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN7)
+
+/* I2C */
+
+#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SCL_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN6)
+#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_I2C1_SDA_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN7)
+#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5)
+
+#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_I2C2_SCL_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN6)
+#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_I2C2_SDA_3 (GPIO_ALT | GPIO_AF0 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTF | GPIO_PIN7)
+
+/* IR */
+
+#define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN13)
+
+/* Clock output */
+
+#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8)
+
+/* SPI */
+
+#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
+
+#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
+#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
+#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
+
+/* SWD */
+
+#define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13)
+
+/* Timers */
+
+#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_TIM1_CH1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_TIM1_CH2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_TIM1_CH3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15)
+#define GPIO_TIM1_CH4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_TIM1_ETR (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12)
+
+#define GPIO_TIM3_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN6)
+#define GPIO_TIM3_CH1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM3_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_TIM3_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN7)
+#define GPIO_TIM3_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM3_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_TIM3_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN8)
+#define GPIO_TIM3_CH3_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_TIM3_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN9)
+#define GPIO_TIM3_CH4_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_TIM3_ETR (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2)
+
+#define GPIO_TIM14_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_TIM14_CH1_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_TIM14_CH1_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN7)
+
+#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_TIM15_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_TIM15_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_TIM15_CH1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_TIM15_CH1N_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN15)
+#define GPIO_TIM15_CH1N_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_TIM15_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_TIM15_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15)
+
+#define GPIO_TIM16_BKIN (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_TIM16_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_TIM16_CH1_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN6)
+
+#define GPIO_TIM17_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_TIM17_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_TIM17_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_TIM17_CH1_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7)
+
+/* USARTs */
+
+#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9)
+
+#define GPIO_USART2_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_USART2_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_USART2_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
+
+#define GPIO_USART3_CK_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12)
+#define GPIO_USART3_CK_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2)
+#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_USART3_RTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_USART3_RTS_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN5)
+#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11)
+#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN4)
+#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10)
+#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN10)
+
+#define GPIO_USART4_CK (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12)
+#define GPIO_USART4_CTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_USART4_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN11)
+#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10)
+#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0)
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H */
--
2.20.1
