Hi Everyone,
This patch fix an issue where Kinetis SPI was transmitting four 0x00
bytes before the actual SPI_SEND() byte.
After some investigation I discovered this detail in the datasheet
about DIS_TXF and DIS_RXF bits: "This bit can be written only when the
MDIS bit is cleared."
BR,
Alan
From 02c135aef5f1d7b63b81dad07a08455e65389ce6 Mon Sep 17 00:00:00 2001
From: Alan Carvalho de Assis <engenhari...@siam.ind.br>
Date: Tue, 4 Feb 2020 15:11:23 -0300
Subject: [PATCH] Fix Kinetis SPI issue: actually TX/RX FIFO wasn't disabled
"When the TX FIFO is disabled, the transmit part of
the module operates as a simplified double-buffered SPI.
This bit can be written only when the MDIS bit is cleared."
---
arch/arm/src/kinetis/kinetis_spi.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/kinetis/kinetis_spi.c
b/arch/arm/src/kinetis/kinetis_spi.c
index 82f2412d3e..84ef79a8c7 100644
--- a/arch/arm/src/kinetis/kinetis_spi.c
+++ b/arch/arm/src/kinetis/kinetis_spi.c
@@ -1182,6 +1182,15 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port)
spi_run(priv, false);
+ /* Read MCR register and clear MDIS (to Enable module clock)
+ * It is necessary because to disable RX and TX FIFO the MDIS
+ * bit should be cleared first.
+ */
+
+ regval = spi_getreg(priv, KINETIS_SPI_MCR_OFFSET);
+ regval &= ~(SPI_MCR_MDIS);
+ spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, regval);
+
/* Configure master mode:
* Master Mode - Enabled
* Continuous SCK - Disabled
@@ -1201,9 +1210,10 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port)
*
*/
- spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, SPI_MCR_MSTR | SPI_MCR_DCONF_SPI |
- SPI_MCR_SMPL_PT_0CLKS | SPI_MCR_PCSIS_MASK | SPI_MCR_HALT|
- SPI_MCR_DIS_RXF | SPI_MCR_DIS_TXF);
+ regval |= SPI_MCR_MSTR | SPI_MCR_DCONF_SPI | SPI_MCR_SMPL_PT_0CLKS |
+ SPI_MCR_PCSIS_MASK | SPI_MCR_HALT | SPI_MCR_DIS_RXF |
+ SPI_MCR_DIS_TXF;
+ spi_putreg(priv, KINETIS_SPI_MCR_OFFSET, regval);
/* Set the initial SPI configuration */
--
2.20.1
