> -----Original Message----- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Shweta Choudaha > Sent: Monday, November 6, 2017 10:25 PM > To: dev@dpdk.org > Cc: Shweta Choudaha > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support > > From: Shweta Choudaha <shweta.choud...@att.com> > > Initialize MDIO read/write functions for backplan port > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO > > Signed-off-by: Shweta Choudaha <shweta.choud...@att.com> > Reviewed-by: Chas Williams <ch...@att.com> > Reviewed-by: Luca Boccassi <bl...@debian.org> > --- > drivers/net/ixgbe/base/ixgbe_x550.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > b/drivers/net/ixgbe/base/ixgbe_x550.c > index 9862391..3f89dc4 100644 > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw > *hw) > } > > switch (hw->device_id) { > + case IXGBE_DEV_ID_X550EM_A_KR_L: Basically this device ID is for a specific SoC platform, there is no external PHY for it. We prefer to NACK it. I added more experts here to answer more questions if you have. Note that they are not working on DPDK, and they are experts on ixgbe NIC/SW. Or we can discuss more if you have any requests to Intel.
Sorry, Helin > case IXGBE_DEV_ID_X550EM_A_1G_T: > case IXGBE_DEV_ID_X550EM_A_1G_T_L: > phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; > -- > 2.1.4
