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Signed-off-by: Beilei Xing <beilei.x...@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index d6b0d50..aba35a5 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1928,6 +1928,31 @@ i40e_apply_link_speed(struct rte_eth_dev *dev)
        return i40e_phy_conf_link(hw, abilities, speed, true);
 }
 
+static void
+i40e_customized_pctype_hash_set(struct i40e_pf *pf, bool enable)
+{
+       struct i40e_hw *hw = I40E_PF_TO_HW(pf);
+       uint64_t hena;
+       int i;
+
+       hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
+       hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
+
+       for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
+               if (pf->customized_pctype[i].valid) {
+                       if (enable)
+                               hena |= 1ULL << pf->customized_pctype[i].pctype;
+                       else
+                               hena &= ~(1ULL <<
+                                         pf->customized_pctype[i].pctype);
+               }
+       }
+
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
+       i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
+       I40E_WRITE_FLUSH(hw);
+}
+
 static int
 i40e_dev_start(struct rte_eth_dev *dev)
 {
@@ -2075,6 +2100,8 @@ i40e_dev_start(struct rte_eth_dev *dev)
                            "please call hierarchy_commit() "
                            "before starting the port");
 
+       i40e_customized_pctype_hash_set(pf, true);
+
        return I40E_SUCCESS;
 
 err_up:
@@ -2155,6 +2182,8 @@ i40e_dev_close(struct rte_eth_dev *dev)
        uint32_t reg;
        int i;
 
+       i40e_customized_pctype_hash_set(pf, false);
+
        PMD_INIT_FUNC_TRACE();
 
        i40e_dev_stop(dev);
-- 
2.5.5

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