> On Sep 14, 2017, at 6:43 AM, Shachar Beiser <shacha...@mellanox.com> wrote:
>
> Signed-off-by: Shachar Beiser <shacha...@mellanox.com>
> ---
[...]
> @@ -550,7 +553,8 @@
> max_wqe -= n;
> if (tso) {
> uint32_t inl =
> - htonl(copy_b | MLX5_INLINE_SEG);
> + rte_cpu_to_be_32(copy_b |
> + MLX5_INLINE_SEG);
Wrong indentation.
[...]
> @@ -605,8 +605,8 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t,
> uint16_t, unsigned int,
> uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
> volatile uint64_t *src = ((volatile uint64_t *)wqe);
>
> - rte_io_wmb();
> - *txq->qp_db = htonl(txq->wqe_ci);
> + rte_wmb();
Look like a mistake when rebasing. This should not be touched by this patch.
> + *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
> /* Ensure ordering between DB record and BF copy. */
> rte_wmb();
> *dst = *src;
--
Thanks,
Yongseok
