Our x86 baseline is to have support for SSE4.2, so therefore there is no point in conditions around the inclusion of SSE1 - SSE4 headers.
Signed-off-by: Bruce Richardson <bruce.richard...@intel.com> --- lib/librte_eal/common/include/arch/x86/rte_vect.h | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/lib/librte_eal/common/include/arch/x86/rte_vect.h b/lib/librte_eal/common/include/arch/x86/rte_vect.h index 1b4b85d..03fc991 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_vect.h +++ b/lib/librte_eal/common/include/arch/x86/rte_vect.h @@ -45,21 +45,7 @@ #if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4)) -#ifdef __SSE__ -#include <xmmintrin.h> -#endif - -#ifdef __SSE2__ -#include <emmintrin.h> -#endif - -#ifdef __SSE3__ -#include <tmmintrin.h> -#endif - -#if defined(__SSE4_2__) || defined(__SSE4_1__) -#include <smmintrin.h> -#endif +#include <smmintrin.h> /* SSE4 */ #if defined(__AVX__) #include <immintrin.h> -- 2.9.4
