> -----Original Message-----
> From: Iremonger, Bernard
> Sent: Wednesday, March 29, 2017 12:21 AM
> To: dev@dpdk.org; Xing, Beilei <beilei.x...@intel.com>; Wu, Jingjing
> <jingjing...@intel.com>
> Cc: Zhang, Helin <helin.zh...@intel.com>; Lu, Wenzhuo
> <wenzhuo...@intel.com>; Iremonger, Bernard
> <bernard.iremon...@intel.com>
> Subject: [PATCH v3 4/5] net/i40e: initialise L3 MAP register
>
> The L3 MAP register is initialised to support QinQ cloud filters.
>
> Signed-off-by: Bernard Iremonger <bernard.iremon...@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index 5a03c7a95..a57b0416d 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -687,6 +687,9 @@ RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "*
> igb_uio | uio_pci_generic | vfio"); #ifndef I40E_GLQF_PIT
> #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
> #endif
> +#ifndef I40E_GLQF_L3_MAP
> +#define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4)) #endif
>
> static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) { @@ -1128,6
> +1131,11 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
> ((hw->nvm.version >> 4) & 0xff),
> (hw->nvm.version & 0xf), hw->nvm.eetrack);
>
> + /* initialise the L3_MAP register */
> + ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
> 0x00000028, NULL);
> + if (ret)
> + PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
> ret);
> +
Hi Bernard,
It's better to put it in i40e_GLQF_reg_init function.
Best Regards
Beilei
> /* Need the special FW version to support floating VEB */
> config_floating_veb(dev);
> /* Clear PXE mode */
> --
> 2.11.0
