Hi Olivier, Looks good in general, some comments from me below. Thanks Konstantin
> > The main changes are: > - reorder structure to increase vector performance on some non-ia > platforms. > - add a 64bits timestamp field in the 1st cache line Wonder why it deserves to be in first cache line? How it differs from seqn below (pure SW stuff right now). > - m->next, m->nb_segs, and m->refcnt are always initialized for mbufs > in the pool, avoiding the need of setting m->next (located in the > 2nd cache line) in the Rx path for mono-segment packets. > - change port and nb_segs to 16 bits Not that I am completely against it, but changing nb_segs to 16 bits seems like an overkill to me. I think we can keep and extra 8bits for something more useful in future. > - move seqn in the 2nd cache line > > Things discussed but not done in the patchset: > - move refcnt and nb_segs to the 2nd cache line: many drivers sets > them in the Rx path, so it could introduce a performance regression, or I wonder can refcnt only be moved into the 2-nd cacheline? As I understand thanks to other change (from above) m->refcnt will already be initialized, so RX code don't need to touch it. Though yes, it still would require changes in all PMDs. > it would require to change all the drivers, which is not an easy task. > - remove the m->port field: too much impact on many examples and libraries, > and some people highlighted they are using it. Ok, but can it be moved into the second cache-line? > - moving m->next in the 1st cache line: there is not enough room, and having > it set to NULL for unused mbuf should remove the need for it. > - merge seqn and timestamp together in a union: we could imagine use cases > were both are activated. There is no flag indicating the presence of seqn, > so it looks preferable to keep them separated for now. > > I made some basic performance tests (ixgbe) and see no regression, but > the patchset requires more testing. > > [1] http://dpdk.org/ml/archives/dev/2016-October/049338.html >
