> 
> To get better performance, Rx bulk alloc recv function will scan 8 descs
> in one time, but the statuses are not consistent on ARM platform because
> the memory allocated for Rx descriptors is cacheable hugepages.
> This patch is to calculate the number of received packets by scan DD bit
> sequentially, and stops when meeting the first packet with DD bit unset.
> 
> Signed-off-by: Jianbo Liu <jianbo....@linaro.org>
> ---
>  drivers/net/ixgbe/ixgbe_rxtx.c | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
> index 36f1c02..613890e 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c
> @@ -1460,17 +1460,19 @@ static inline int __attribute__((always_inline))
>       for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
>            i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
>               /* Read desc statuses backwards to avoid race condition */
> -             for (j = LOOK_AHEAD-1; j >= 0; --j)
> +             for (j = 0; j < LOOK_AHEAD; j++)
>                       s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
> 
> -             for (j = LOOK_AHEAD - 1; j >= 0; --j)
> -                     pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
> -                                                    lo_dword.data);
> +             rte_smp_rmb();
> 
>               /* Compute how many status bits were set */
> -             nb_dd = 0;
> -             for (j = 0; j < LOOK_AHEAD; ++j)
> -                     nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
> +             for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
> +                             (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
> +                     ;
> +
> +             for (j = 0; j < nb_dd; j++)
> +                     pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
> +                                                    lo_dword.data);
> 
>               nb_rx += nb_dd;
> 
> --

Acked-by: Konstantin Ananyev <konstantin.anan...@intel.com>

> 1.8.3.1

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