The previous version relied on the fact that DMA sync for device and PIO write barrier in pair. Now each does its job.
Signed-off-by: Andrew Rybchenko <arybche...@solarflare.com> --- drivers/net/sfc/efsys.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/sfc/efsys.h b/drivers/net/sfc/efsys.h index a024b6c..60829be 100644 --- a/drivers/net/sfc/efsys.h +++ b/drivers/net/sfc/efsys.h @@ -612,7 +612,7 @@ /* BARRIERS */ #define EFSYS_MEM_READ_BARRIER() rte_rmb() -#define EFSYS_PIO_WRITE_BARRIER() rte_wmb() +#define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb() /* DMA SYNC */ @@ -623,7 +623,9 @@ */ #define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0) -#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) ((void)0) + +/* Just avoid store and compiler (impliciltly) reordering */ +#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb() /* TIMESTAMP */ -- 1.8.2.3
