Signed-off-by: Elad Persiko <ela...@mellanox.com>
---
doc/guides/nics/mlx5.rst | 6 ++++++
drivers/net/mlx5/mlx5.c | 17 ++++++++++++++++-
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_txq.c | 4 +++-
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index a41c432..816075a 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -188,6 +188,12 @@ Run-time configuration
It is currently only supported on the ConnectX-4 Lx and ConnectX-5
families of adapters. Enabled by default.
+- ``txq_lso_en`` parameter [int]
+
+ A nonzero value enables TCP Segmentation Offloading (in hardware) on tx
+ side. It saves CPU time and PCI bandwidth.
+
+ Enabled by default.
Prerequisites
-------------
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 6293c1f..55c5b87 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -84,6 +84,9 @@
/* Device parameter to enable multi-packet send WQEs. */
#define MLX5_TXQ_MPW_EN "txq_mpw_en"
+/* Device parameter to enable LSO. */
+#define MLX5_TXQ_LSO_EN "txq_lso_en"
+
/**
* Retrieve integer value from environment variable.
*
@@ -287,6 +290,8 @@
priv->txqs_inline = tmp;
} else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
priv->mps &= !!tmp; /* Enable MPW only if HW supports */
+ } else if (strcmp(MLX5_TXQ_LSO_EN, key) == 0) {
+ priv->lso &= !!tmp;
} else {
WARN("%s: unknown parameter", key);
return -EINVAL;
@@ -312,6 +317,7 @@
MLX5_RXQ_CQE_COMP_EN,
MLX5_TXQ_INLINE,
MLX5_TXQS_MIN_INLINE,
+ MLX5_TXQ_LSO_EN,
MLX5_TXQ_MPW_EN,
NULL,
};
@@ -429,7 +435,7 @@
mps = 0;
}
INFO("PCI information matches, using device \"%s\""
- " (SR-IOV: %s, MPS: %s)",
+ " (SR-IOV: %s, LSO: true, MPS: %s)",
list[i]->name,
sriov ? "true" : "false",
mps ? "true" : "false");
@@ -474,8 +480,11 @@
IBV_EXP_DEVICE_ATTR_RX_HASH |
IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |
IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |
+ IBV_EXP_DEVICE_ATTR_TSO_CAPS |
0;
+ exp_device_attr.tso_caps.max_tso = 262144;
+ exp_device_attr.tso_caps.supported_qpts = IBV_QPT_RAW_ETH;
DEBUG("using port %u (%08" PRIx32 ")", port, test);
ctx = ibv_open_device(ibv_dev);
@@ -525,6 +534,7 @@
priv->port = port;
priv->pd = pd;
priv->mtu = ETHER_MTU;
+ priv->lso = 1; /* Enabled by default. */
priv->mps = mps; /* Enable MPW by default if supported. */
priv->cqe_comp = 1; /* Enable compression by default. */
err = mlx5_args(priv, pci_dev->device.devargs);
@@ -580,6 +590,11 @@
err = ENOTSUP;
goto port_error;
}
+ if (priv->lso && priv->mps) {
+ ERROR("LSO and MPS can't coexists");
+ err = ENOTSUP;
+ goto port_error;
+ }
/* Allocate and register default RSS hash keys. */
priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
sizeof((*priv->rss_conf)[0]), 0);
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index ee62e04..a163983 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -116,6 +116,7 @@ struct priv {
unsigned int hw_padding:1; /* End alignment padding is supported. */
unsigned int sriov:1; /* This is a VF or PF with VF devices. */
unsigned int mps:1; /* Whether multi-packet send is supported. */
+ unsigned int lso:1; /* Whether lso is supported. */
unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */
unsigned int pending_alarm:1; /* An alarm is pending. */
unsigned int txq_inline; /* Maximum packet size for inlining. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 951e50a..de9f494 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -337,8 +337,10 @@
.sq_sig_all = 0,
.pd = priv->pd,
.res_domain = tmpl.rd,
+ .max_tso_header = 128, // ETH/IPv4/TCP header example
.comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
- IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
+ IBV_EXP_QP_INIT_ATTR_RES_DOMAIN |
+ IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER),
};
if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
tmpl.txq.max_inline =
--
1.8.3.1
