On Wed, Jan 04, 2017 at 03:39:14PM +0530, Jerin Jacob wrote:
> On Tue, Jan 03, 2017 at 03:55:45PM +0800, Jianbo Liu wrote:
> > On 27 December 2016 at 17:49, Jerin Jacob
> > <jerin.ja...@caviumnetworks.com> wrote:
> > > Change rte_?wb definitions to macros in order to
> >
> > use rte_*mb?
>
> IMHO, regex ? is appropriate here.
> https://en.wikipedia.org/wiki/Regular_expression
>
The APIs you're changing are:
> +#define rte_mb() dsb(sy)
> +#define rte_wmb() dsb(st)
> +#define rte_rmb() dsb(ld)
If it's a regex, shouldn't it be: rte_[wr]?mb or rte_.?mb
If ? is a wildcard used by shell, it should at least be: rte_?mb
But rte_*mb is easier to recognize, and matches all of them. :-)
Best regards,
Tiwei Bie
> >
> > > keep consistent with other barrier definitions in
> > > the file.
> > >
> > > Suggested-by: Jianbo Liu <jianbo....@linaro.org>
> > > Signed-off-by: Jerin Jacob <jerin.ja...@caviumnetworks.com>
> > > ---
> > > .../common/include/arch/arm/rte_atomic_64.h | 36
> > > ++--------------------
> > > 1 file changed, 3 insertions(+), 33 deletions(-)
> > >
> > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > index ef0efc7..dc3a0f3 100644
> > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > @@ -46,41 +46,11 @@ extern "C" {
> > > #define dsb(opt) { asm volatile("dsb " #opt : : : "memory"); }
> > > #define dmb(opt) { asm volatile("dmb " #opt : : : "memory"); }
> > >
> > > -/**
> > > - * General memory barrier.
> > > - *
> > > - * Guarantees that the LOAD and STORE operations generated before the
> > > - * barrier occur before the LOAD and STORE operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> > > -static inline void rte_mb(void)
> > > -{
> > > - dsb(sy);
> > > -}
> > > +#define rte_mb() dsb(sy)
> > >
> > > -/**
> > > - * Write memory barrier.
> > > - *
> > > - * Guarantees that the STORE operations generated before the barrier
> > > - * occur before the STORE operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> > > -static inline void rte_wmb(void)
> > > -{
> > > - dsb(st);
> > > -}
> > > +#define rte_wmb() dsb(st)
> > >
> > > -/**
> > > - * Read memory barrier.
> > > - *
> > > - * Guarantees that the LOAD operations generated before the barrier
> > > - * occur before the LOAD operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> >
> > How about keep the comments for all these macros?
>
> lib/librte_eal/common/include/generic/rte_atomic.h file has description
> for all the barriers.All other arch are doing in the same-way.
>
> >
> > > -static inline void rte_rmb(void)
> > > -{
> > > - dsb(ld);
> > > -}
> > > +#define rte_rmb() dsb(ld)
> > >
> > > #define rte_smp_mb() dmb(ish)
> > >
> > > --
> > > 2.5.5
> > >
