> -----Original Message----- > From: Sexton, Rory > Sent: Friday, December 9, 2016 10:03 PM > To: Wu, Jingjing <jingjing...@intel.com> > Cc: dev@dpdk.org; Marjanovic, Nemanja <nemanja.marjano...@intel.com>; > Mcnamara, John <john.mcnam...@intel.com> > Subject: RE: [PATCH v1] net/i40e: set no drop for traffic class > > Hi Jingjing, > > Yes PRTDCB_TC2PFC is used to control pfc for each TC however we have > noticed other advantages of using the register. > By setting the register explicitly by doing the "I40E_WRITE_REG(hw, 0x1c0980, > 0xff);" it allows for packets to be temporarily stored on the NICs RX SRAM > until there is space for them on SW descriptor ring versus dropping them > when the SW ring becomes full. This also allows for larger burst handling. It > also means SW doesn't have to be as quick to empty the DRAM based > descriptor rings, allowing more processing on cores. > > I have tested using the ETH_DCB_PFC_SUPPORT flag in > rte_eth_conf.dcb_capability_en and rte_eth_dcb_rx_conf.nb_tcs. > This results in the NIC's RX SRAM not being used and if there is no space on > SW descriptor ring for packet it is dropped.
Besides ETH_DCB_PFC_SUPPORT, ETH_MQ_RX_DCB_FLAG is also required in dev_conf.rxmode.mq_mode. After doing that, you will find register PRTDCB_TC2PFC is also changed. If you don't want to enable DCB, why not just implement that function "i40e_priority_flow_ctrl_set"? You can change the register in this function without define a new API. > The advantages of using the PRTDCB_TC2PFC explicitly is that there will be no > packet loss and descriptor rings do not need to be modified (can be left at > 128 for rx and 512 for tx as default settings for apps). Enabling via this > register allows Burst handling to be within the NIC Rx Buffer and SW rings > combined. > At the moment for tests the rx and tx descriptor rings have to be increased > to 2048 to eliminate packet loss. > > Ideally it would be an optional setting as using it may increase the max > latency. > Thanks for the clarification. Thanks Jingjing