> From: Ferruh Yigit [mailto:ferruh.yi...@intel.com] > Sent: Friday, December 23, 2016 7:39 AM > > On 12/3/2016 9:11 AM, Rasesh Mody wrote: > > Add PCI IDs for new asic type (defined as CHIP_NUM_AH_xxx). > > It supports 50G, 40G, 25G and 10G speeds. > > > > Signed-off-by: Rasesh Mody <rasesh.m...@cavium.com> > > --- > > drivers/net/qede/base/ecore_dev.c | 7 +++++- > > drivers/net/qede/qede_ethdev.c | 29 ++++++++++++++++++------ > > drivers/net/qede/qede_ethdev.h | 47 ++++++++++++++++++++++++--- > ------------ > > 3 files changed, 57 insertions(+), 26 deletions(-) > > > > diff --git a/drivers/net/qede/base/ecore_dev.c > > b/drivers/net/qede/base/ecore_dev.c > > index 5a29c45b..03620d94 100644 > > --- a/drivers/net/qede/base/ecore_dev.c > > +++ b/drivers/net/qede/base/ecore_dev.c > > @@ -2365,7 +2365,12 @@ static enum _ecore_status_t > > ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, #endif > > > > for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { > > - rc = ecore_hw_set_resc_info(p_hwfn, res_id, > drv_resc_alloc); > > + /* @@@TMP for AH: > > + * Force the driver's default resource allocation in case there > > + * is a diff with the MFW allocation value. > > + */ > > + rc = ecore_hw_set_resc_info(p_hwfn, res_id, > > + b_ah || drv_resc_alloc); > > Just to double check, is above code piece is related to the "add PCI ids for > new chip variant" ?
Yes, that is correct. In case of new chip variant AH, we force the driver's default resource allocation if it differs from management firmware allocation value. > > if (rc != ECORE_SUCCESS) > > return rc; > > } > <...>
