On 21 December 2016 at 19:03, Bruce Richardson <bruce.richard...@intel.com> wrote: > On Wed, Dec 21, 2016 at 03:38:51PM +0530, Jerin Jacob wrote: >> On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote: >> >> Hi Jianbo, >> >> > vPMD will check 4 descriptors in one time, but the statuses are not >> > consistent >> > because the memory allocated for RX descriptors is cacheable huagepage. >> Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages? > > This is not a problem on IA, because the instruction ordering rules on > IA guarantee that the reads will be done in the correct program order, > and we never get stale cache data. >
Yes, I think it's an issue for ARM arch. It's because more than one cacheline-sized data (4/8 descriptors can be in two cachelines) will be read at one time in bulk alloc RX or vPMD. There is the same issue for i40e, I'll send the same patch later.
