Add code branch for 25G link speed,
so 25G device will be functional.
Signed-off-by: Zhang Qi <qi.z.zhang at intel.com>
---
v6:
- rebase to dpdk-next-net/rel_16_11.
v3:
- add PHY type check macro for 25G devices.
- use PHY type to check if device support 25G.
drivers/net/i40e/i40e_ethdev.c | 22 ++++++++++++++++++----
drivers/net/i40e/i40e_ethdev.h | 6 ++++++
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index a5669a5..e772e4e 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1586,6 +1586,8 @@ i40e_parse_link_speeds(uint16_t link_speeds)
if (link_speeds & ETH_LINK_SPEED_40G)
link_speed |= I40E_LINK_SPEED_40GB;
+ if (link_speeds & ETH_LINK_SPEED_25G)
+ link_speed |= I40E_LINK_SPEED_25GB;
if (link_speeds & ETH_LINK_SPEED_20G)
link_speed |= I40E_LINK_SPEED_20GB;
if (link_speeds & ETH_LINK_SPEED_10G)
@@ -1611,6 +1613,7 @@ i40e_phy_conf_link(struct i40e_hw *hw,
I40E_AQ_PHY_FLAG_PAUSE_RX |
I40E_AQ_PHY_FLAG_LOW_POWER;
const uint8_t advt = I40E_LINK_SPEED_40GB |
+ I40E_LINK_SPEED_25GB |
I40E_LINK_SPEED_10GB |
I40E_LINK_SPEED_1GB |
I40E_LINK_SPEED_100MB;
@@ -1663,7 +1666,8 @@ i40e_apply_link_speed(struct rte_eth_dev *dev)
struct rte_eth_conf *conf = &dev->data->dev_conf;
speed = i40e_parse_link_speeds(conf->link_speeds);
- abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+ if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+ abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
abilities |= I40E_AQ_PHY_AN_ENABLED;
abilities |= I40E_AQ_PHY_LINK_ENABLED;
@@ -1765,7 +1769,8 @@ i40e_dev_start(struct rte_eth_dev *dev)
/* Apply link configure */
if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
- ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
+ ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
+ ETH_LINK_SPEED_40G)) {
PMD_DRV_LOG(ERR, "Invalid link setting");
goto err_up;
}
@@ -1985,9 +1990,11 @@ static int
i40e_dev_set_link_down(struct rte_eth_dev *dev)
{
uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
- uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+ uint8_t abilities = 0;
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+ abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
return i40e_phy_conf_link(hw, abilities, speed);
}
@@ -2045,6 +2052,9 @@ i40e_dev_link_update(struct rte_eth_dev *dev,
case I40E_LINK_SPEED_20GB:
link.link_speed = ETH_SPEED_NUM_20G;
break;
+ case I40E_LINK_SPEED_25GB:
+ link.link_speed = ETH_SPEED_NUM_25G;
+ break;
case I40E_LINK_SPEED_40GB:
link.link_speed = ETH_SPEED_NUM_40G;
break;
@@ -2647,6 +2657,9 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
/* For XL710 */
dev_info->speed_capa = ETH_LINK_SPEED_40G;
+ else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+ /* For XXL710 */
+ dev_info->speed_capa = ETH_LINK_SPEED_25G;
else
/* For X710 */
dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
@@ -8307,7 +8320,8 @@ i40e_configure_registers(struct i40e_hw *hw)
for (i = 0; i < RTE_DIM(reg_table); i++) {
if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
- if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) /*
For XL710 */
+ if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /*
For XL710 */
+ I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /*
For XXL710 */
reg_table[i].val =
I40E_GL_SWR_PM_UP_THR_SF_VALUE;
else /* For X710 */
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index f3bff98..57a8ae1 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -765,4 +765,10 @@ i40e_calc_itr_interval(int16_t interval)
((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
+#define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
+ (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
+ ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
+
#endif /* _I40E_ETHDEV_H_ */
--
2.7.4
