Hi Adrien, On 14 September 2016 at 16:30, Adrien Mazarguil <adrien.mazarguil at 6wind.com> wrote:
> Your interpretation is correct (this is intentional and not a bug). > Thanks very much for clarifying. This is interesting to me because I am also working on a ConnectX-4 (Lx) driver based on the newly released driver interface specification [1] and I am wondering how interested I should be in this MPW feature that is currently not documented. In the event successive packets share a few properties (length, number of > segments, offload flags), these can be factored out as an optimization to > lower the amount of traffic on the PCI bus. This feature is currently > supported by the ConnectX-4 Lx family of adapters. > I have a concern here that I hope you will forgive me for voicing. This optimization seems to run the risk of inflating scores on constant-packet-size IXIA-style benchmarks like [2] and making them less useful for predicting real-world performance. That seems like a negative to me as an application developer. I wonder if I am overlooking some practical benefits that motivate implementing this in silicon and in the driver and enabling it by default? Cheers, -Luke [1] http://www.mellanox.com/related-docs/user_manuals/Ethernet_Adapters_Programming_Manual.pdf [2] https://www.mellanox.com/blog/2016/06/performance-beyond-numbers-stephen-curry-style-server-io/
