I wanna create for example 3 different packets in core_0 as master and store them one by one in share memory(rte_ring), then the core_1 as slave read them and do function on them (ex. P1+P2+P3) and again store in share memory, finally the core_0 read the packets from share memory and compare them with whatever expected :) As I said and you mentioned is the same? :)
On 8 March 2016 at 00:35, Hamed Zaghaghi <hamed.zaghaghi at gmail.com> wrote: > Hi, > > If I understood well you need to do these tasks: > 1. Packet crafting (I think that DPDK has no functions for this task) > 2. Store packets (DPDK has (rte_mbuf)[ > http://dpdk.org/doc/api/rte__mbuf_8h.html]) > 3. Share between lcores (DPDK offers rte_ring) > > > > On Tue, Mar 8, 2016 at 8:45 AM Mahdi Moradmand Badie < > mahdi.mbadie at gmail.com> wrote: > >> Dear Hamed, >> >> First of all thank you so much for your kindly reply, >> >> It's the primary part of the big project, in order to be more familiar >> with DPDK, >> I have to implement the mentioned framework by use of DPDK, >> And finally we wanna implement the cache locking approach (via help of >> features like Cache Allocation Technology(CAT), Cache Monitoring Technology >> (CMT)) in Xeon processor (my supervisor told me this simple exercise >> will be helpful to do the final part) in such a way we could dedicate a >> specific part of shared memory (L3) to each core which the other don't >> access to it. >> Obviously using of DPDK with Xeon which both are from "Intel", is >> considered as strength point. >> >> I hope this was more clear :) >> >> On 7 March 2016 at 23:56, Hamed Zaghaghi <hamed.zaghaghi at gmail.com> >> wrote: >> >>> Hi Mahdi, >>> >>> Why do you want to use DPDK when you don't use NIC? You can do what you >>> want outside of DPDK. >>> >>> Regards, >>> Hamed Zaghaghi >>> >>> On Tue, Mar 8, 2016 at 12:16 AM Mahdi Moradmand Badie < >>> mahdi.mbadie at gmail.com> wrote: >>> >>>> Dear All, >>>> I am Mahdi and I am new in DPDK, >>>> I wanna generate for example 3 different packets in core0 as master >>>> write >>>> it to share memory (L3), then core1 as slave read this packets, change >>>> them >>>> with for example function1 and write again in share memory (L3) and >>>> finally >>>> check the result with whatever I expect. >>>> The most important thing is that I don't wanna use NIC and I don't know >>>> for >>>> working with cores how I can write/read to/from them, I mean with which >>>> template and sequence??? >>>> Thanks in advance, >>>> >>> >> >> >> -- >> M at hdi Mor at dm@nd B at die >> > -- M at hdi Mor at dm@nd B at die
