The second pre-cursor tap of the 25G E56 PHY and the advertised 40G
backplane capability selector were both added without any value ever
being assigned, so hw->phy.ffe_pre2 and hw->phy.bp_capa stayed at
zero:
- With ffe_set enabled, txgbe_e56_tx_ffe_cfg() programmed a zero
second pre-cursor tap instead of the recommended value for the
module.
- txgbe_e56_set_phy_link_mode() could only advertise KR4+CR4: the
KR4-only and CR4-only capabilities selected by bp_capa were
unreachable.
Assign the recommended defaults and add the ffe_pre2 and bp_capa
device arguments so that both can be configured. The NIC guide and
the release notes document the two new devargs.
Fixes: 6104fd11089d ("net/txgbe: fix link stability for 25G NIC")
Fixes: 234ce0d1fa9d ("net/txgbe: fix link stability for Amber-Lite backplane
mode")
Cc: [email protected]
Signed-off-by: Zaiyu Wang <[email protected]>
---
doc/guides/nics/txgbe.rst | 11 +++++++++++
doc/guides/rel_notes/release_26_11.rst | 8 ++++++++
drivers/net/txgbe/base/txgbe_type.h | 6 +++++-
drivers/net/txgbe/txgbe_ethdev.c | 23 +++++++++++++++++++----
4 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst
index 90c55141f1..d56fb3b99a 100644
--- a/doc/guides/nics/txgbe.rst
+++ b/doc/guides/nics/txgbe.rst
@@ -142,6 +142,11 @@ Please note that following ``devargs`` are only set for
backplane NICs.
PHY parameter used for user debugging. Setting other values to
take effect requires setting the ``ffe_set``.
+- ``ffe_pre2`` (default **0**)
+
+ PHY parameter used for user debugging, only for the Amber-Lite E56 PHY.
+ Setting other values to take effect requires setting the ``ffe_set``.
+
- ``ffe_post`` (default **44**)
PHY parameter used for user debugging. Setting other values to
@@ -177,6 +182,12 @@ Please note that following ``devargs`` are only set for
Amber-Lite NICs.
In this mode, the hardware merges and writes back a group of RX descriptors
together to reduce memory access times, which helps improve performance.
+- ``bp_capa`` (default **0**)
+
+ Backplane capability selection for the 40G NIC. Set 0 for both
+ 40GBASE-KR4 and 40GBASE-CR4, set 1 for 40GBASE-KR4 only, set 2 for
+ 40GBASE-CR4 only.
+
Driver compilation and testing
------------------------------
diff --git a/doc/guides/rel_notes/release_26_11.rst
b/doc/guides/rel_notes/release_26_11.rst
index 4b3e5d995c..461e26459b 100644
--- a/doc/guides/rel_notes/release_26_11.rst
+++ b/doc/guides/rel_notes/release_26_11.rst
@@ -56,6 +56,14 @@ New Features
=======================================================
+* **Updated Wangxun txgbe driver.**
+
+ * Added the ``ffe_pre2`` device argument to tune the second pre-cursor
+ tap of the Amber-Lite E56 PHY (requires ``ffe_set``).
+ * Added the ``bp_capa`` device argument to select the advertised
+ backplane capability on the 40G NIC
+ (0 for 40GBASE-KR4 + 40GBASE-CR4, 1 for KR4 only, 2 for CR4 only).
+
Removed Items
-------------
diff --git a/drivers/net/txgbe/base/txgbe_type.h
b/drivers/net/txgbe/base/txgbe_type.h
index 4ed4737043..f56cd70c6f 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -741,7 +741,7 @@ struct txgbe_phy_info {
u16 ffe_set;
u32 ffe_main;
u32 ffe_pre;
- u32 ffe_pre2;
+ u32 ffe_pre2; /* only for the Amber-Lite E56 PHY */
u32 ffe_post;
u16 fec_mode;
u16 bp_capa;
@@ -754,12 +754,14 @@ struct txgbe_phy_info {
#define TXGBE_DEVARG_FFE_SET "ffe_set"
#define TXGBE_DEVARG_FFE_MAIN "ffe_main"
#define TXGBE_DEVARG_FFE_PRE "ffe_pre"
+#define TXGBE_DEVARG_FFE_PRE2 "ffe_pre2"
#define TXGBE_DEVARG_FFE_POST "ffe_post"
#define TXGBE_DEVARG_FDIR_PBALLOC "pkt-filter-size"
#define TXGBE_DEVARG_FDIR_DROP_QUEUE "pkt-filter-drop-queue"
#define TXGBE_DEVARG_TX_HEAD_WB "tx_headwb"
#define TXGBE_DEVARG_TX_HEAD_WB_SIZE "tx_headwb_size"
#define TXGBE_DEVARG_RX_DESC_MERGE "rx_desc_merge"
+#define TXGBE_DEVARG_BP_CAPA "bp_capa"
static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_BP_AUTO,
@@ -769,12 +771,14 @@ static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_FFE_SET,
TXGBE_DEVARG_FFE_MAIN,
TXGBE_DEVARG_FFE_PRE,
+ TXGBE_DEVARG_FFE_PRE2,
TXGBE_DEVARG_FFE_POST,
TXGBE_DEVARG_FDIR_PBALLOC,
TXGBE_DEVARG_FDIR_DROP_QUEUE,
TXGBE_DEVARG_TX_HEAD_WB,
TXGBE_DEVARG_TX_HEAD_WB_SIZE,
TXGBE_DEVARG_RX_DESC_MERGE,
+ TXGBE_DEVARG_BP_CAPA,
NULL
};
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index b27a5af062..72264befae 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -540,13 +540,20 @@ txgbe_parse_devargs(struct rte_eth_dev *dev)
u16 tx_headwb = 1;
u16 tx_headwb_size = 16;
u16 rx_desc_merge = 1;
+ u16 bp_capa = 0;
- /* The 40G NIC holds one FFE byte per lane, so the E56 PHY defaults
- * below are later replicated over the four lanes.
+ /* The E56 PHY needs its own FFE defaults, as the ones above only
+ * apply to the Sapphire PHY.
*/
- if (hw->mac.type == txgbe_mac_aml40) {
+ if (hw->mac.type == txgbe_mac_aml) {
+ ffe_main = S25G_TX_FFE_CFG_DAC_MAIN;
+ ffe_pre = S25G_TX_FFE_CFG_DAC_PRE1;
+ ffe_pre2 = S25G_TX_FFE_CFG_DAC_PRE2;
+ ffe_post = S25G_TX_FFE_CFG_DAC_POST;
+ } else if (hw->mac.type == txgbe_mac_aml40) {
ffe_main = S40G_TX_FFE_CFG_MAIN & 0xFF;
ffe_pre = S40G_TX_FFE_CFG_PRE1 & 0xFF;
+ ffe_pre2 = S40G_TX_FFE_CFG_PRE2 & 0xFF;
ffe_post = S40G_TX_FFE_CFG_POST & 0xFF;
}
@@ -571,6 +578,8 @@ txgbe_parse_devargs(struct rte_eth_dev *dev)
&txgbe_handle_devarg, &ffe_main);
rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
&txgbe_handle_devarg, &ffe_pre);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE2,
+ &txgbe_handle_devarg, &ffe_pre2);
rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
&txgbe_handle_devarg, &ffe_post);
rte_kvargs_process(kvlist, TXGBE_DEVARG_FDIR_PBALLOC,
@@ -583,6 +592,8 @@ txgbe_parse_devargs(struct rte_eth_dev *dev)
&txgbe_handle_devarg, &tx_headwb_size);
rte_kvargs_process(kvlist, TXGBE_DEVARG_RX_DESC_MERGE,
&txgbe_handle_devarg, &rx_desc_merge);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_CAPA,
+ &txgbe_handle_devarg, &bp_capa);
rte_kvargs_free(kvlist);
null:
@@ -596,7 +607,9 @@ txgbe_parse_devargs(struct rte_eth_dev *dev)
hw->phy.ffe_set = ffe_set;
hw->phy.ffe_main = ffe_main;
hw->phy.ffe_pre = ffe_pre;
+ hw->phy.ffe_pre2 = ffe_pre2;
hw->phy.ffe_post = ffe_post;
+ hw->phy.bp_capa = bp_capa;
/* The 40G PHY expects one FFE byte per lane. */
if (hw->mac.type == txgbe_mac_aml40) {
@@ -6519,12 +6532,14 @@ RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
TXGBE_DEVARG_FFE_SET "=<0-4>"
TXGBE_DEVARG_FFE_MAIN "=<uint16>"
TXGBE_DEVARG_FFE_PRE "=<uint16>"
+ TXGBE_DEVARG_FFE_PRE2 "=<uint16>"
TXGBE_DEVARG_FFE_POST "=<uint16>"
TXGBE_DEVARG_FDIR_PBALLOC "=<0|1|2>"
TXGBE_DEVARG_FDIR_DROP_QUEUE "=<uint8>"
TXGBE_DEVARG_TX_HEAD_WB "=<0|1>"
TXGBE_DEVARG_TX_HEAD_WB_SIZE "=<1|16>"
- TXGBE_DEVARG_RX_DESC_MERGE "=<0|1>");
+ TXGBE_DEVARG_RX_DESC_MERGE "=<0|1>"
+ TXGBE_DEVARG_BP_CAPA "=<0|1|2>");
RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE);
RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE);
--
2.55.0.windows.2
