On Mon, 6 Jul 2026 14:54:14 +0530 Shreesh Adiga <[email protected]> wrote:
> Add a 64-byte loop that maintains 4 fold registers and processes > 64 bytes at a time. The 4x fold registers is then reduced to 16 byte > single fold, similar to x86 SSE implementation. This technique is > described in the paper by Intel: > "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction" > > This results in roughly 2x performance improvement due to better ILP > for large input sizes like 1024 observed on Cortex-X925. > > Also removed the special handling of len 16 to 31 similar to x86 SSE > implementation. > > Signed-off-by: Shreesh Adiga <[email protected]> > --- Applied to next-net
