From: Satheesh Paul <[email protected]> Support for flow aggregator enqueue profiles.
Signed-off-by: Satheesh Paul <[email protected]> --- drivers/common/cnxk/roc_mbox.h | 57 +++++++++++ drivers/common/cnxk/roc_nix.c | 41 ++++++++ drivers/common/cnxk/roc_nix.h | 2 + drivers/common/cnxk/roc_nix_flow_vec.h | 99 +++++++++++++++++++ drivers/common/cnxk/roc_npc_priv.h | 3 + .../common/cnxk/roc_platform_base_symbols.c | 1 + 6 files changed, 203 insertions(+) create mode 100644 drivers/common/cnxk/roc_nix_flow_vec.h diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 52ecde6563..814999722f 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -359,6 +359,8 @@ struct mbox_msghdr { msg_rsp) \ M(NIX_RX_INL_QUEUE_CFG, 0x8033, nix_rx_inl_queue_cfg, \ nix_rx_inline_qcfg_req, msg_rsp) \ + M(NIX_AF_RX_FLOW_VEC_CTRL_SET, 0x8034, nix_af_rx_flow_vec_ctrl_set, \ + nix_af_rx_flow_vec_ctrl_write_req, msg_rsp) \ /* MCS mbox IDs (range 0xa000 - 0xbFFF) */ \ M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ @@ -2773,6 +2775,61 @@ struct npc_cn20k_mcam_write_entry_req { uint64_t __io reserved; /* reserved for future use */ }; +union nix_af_rx_flow_vec_ctrl0x { + struct nix_af_rx_flow_vec_ctrl0x_s { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint64_t __io reserved : 14; + uint64_t __io sov_offset : 8; + uint64_t __io sov_mask : 16; + uint64_t __io sov_inv : 1; + uint64_t __io eov_offset : 8; + uint64_t __io eov_mask : 16; + uint64_t __io eov_inv : 1; +#else + uint64_t __io eov_inv : 1; + uint64_t __io eov_mask : 16; + uint64_t __io eov_offset : 8; + uint64_t __io sov_inv : 1; + uint64_t __io sov_mask : 16; + uint64_t __io sov_offset : 8; + uint64_t __io reserved : 14; +#endif + } __attribute__((__packed__)) s; + uint64_t __io val; +}; + +union nix_af_rx_flow_vec_ctrl1x { + struct nix_af_rx_flow_vec_ctrl1x_s { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint64_t __io reserved : 35; + uint64_t __io valid : 1; + uint64_t __io lid : 3; + uint64_t __io ltype_match : 4; + uint64_t __io ltype_mask : 4; + uint64_t __io ver_offset : 9; + uint64_t __io ver_match : 4; + uint64_t __io ver_mask : 4; +#else + uint64_t __io ver_mask : 4; + uint64_t __io ver_match : 4; + uint64_t __io ver_offset : 9; + uint64_t __io ltype_mask : 4; + uint64_t __io ltype_match : 4; + uint64_t __io lid : 3; + uint64_t __io valid : 1; + uint64_t __io reserved : 35; +#endif + } __attribute__((__packed__)) s; + uint64_t __io val; +}; + +#define NIX_AF_RX_FLOW_VEC_CTRL_MAX 4 +struct nix_af_rx_flow_vec_ctrl_write_req { + struct mbox_msghdr hdr; + union nix_af_rx_flow_vec_ctrl0x ctrl0x[NIX_AF_RX_FLOW_VEC_CTRL_MAX]; + union nix_af_rx_flow_vec_ctrl1x ctrl1x[NIX_AF_RX_FLOW_VEC_CTRL_MAX]; +}; + /* Enable/Disable a given entry */ struct npc_mcam_ena_dis_entry_req { struct mbox_msghdr hdr; diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 477c7d5ca0..8e3903051d 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -3,6 +3,7 @@ */ #include "roc_api.h" +#include "roc_nix_flow_vec.h" #include "roc_priv.h" bool @@ -524,7 +525,15 @@ roc_nix_dev_init(struct roc_nix *roc_nix) roc_nix_get_hw_info(roc_nix); nix->dev.drv_inited = true; + if (roc_model_is_cn20k()) { + rc = roc_nix_af_rx_flow_vec_ctrl_set(roc_nix); + if (rc) + goto tm_conf_fini; + } + return 0; +tm_conf_fini: + nix_tm_conf_fini(roc_nix); unregister_irqs: nix_unregister_irqs(nix); lf_detach: @@ -588,3 +597,35 @@ roc_nix_max_rep_count(struct roc_nix *roc_nix) mbox_put(mbox); return rc; } + +static int +nix_af_rx_flow_vec_ctrl_set(struct mbox *mbox) +{ + struct nix_af_rx_flow_vec_ctrl_write_req *req; + struct nix_af_rx_flow_vec_ctrl_write_rsp *rsp; + int rc = -ENOSPC; + + req = mbox_alloc_msg_nix_af_rx_flow_vec_ctrl_set(mbox_get(mbox)); + if (req == NULL) + goto exit; + + memcpy(&req->ctrl0x, nix_flow_ctrl0, sizeof(nix_flow_ctrl0)); + memcpy(&req->ctrl1x, nix_flow_ctrl1, sizeof(nix_flow_ctrl1)); + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + +exit: + mbox_put(mbox); + return rc; +} + +int +roc_nix_af_rx_flow_vec_ctrl_set(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct dev *dev = &nix->dev; + + return nix_af_rx_flow_vec_ctrl_set(dev->mbox); +} diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 0b1e501b16..35a90f982b 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -1052,6 +1052,8 @@ int __roc_api roc_nix_npc_rx_ena_dis(struct roc_nix *roc_nix, bool enable); int __roc_api roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool mcast_enable, bool prom_enable); +int __roc_api roc_nix_af_rx_flow_vec_ctrl_set(struct roc_nix *roc_nix); + /* RSS */ void __roc_api roc_nix_rss_key_default_fill(struct roc_nix *roc_nix, uint8_t key[ROC_NIX_RSS_KEY_LEN]); diff --git a/drivers/common/cnxk/roc_nix_flow_vec.h b/drivers/common/cnxk/roc_nix_flow_vec.h new file mode 100644 index 0000000000..72dbf44292 --- /dev/null +++ b/drivers/common/cnxk/roc_nix_flow_vec.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_NIX_FLOW_VEC_H_ +#define _ROC_NIX_FLOW_VEC_H_ + +#define IPV4_SOV_OFFSET 6 +#define IPV4_SOV_MASK 0x1FFF +#define IPV4_EOV_OFFSET 6 +#define IPV4_EOV_MASK 0x2000 + +#define IPV6_SOV_OFFSET 0x2A +#define IPV6_SOV_MASK 0xFFF8 +#define IPV6_EOV_OFFSET 0x2A +#define IPV6_EOV_MASK 0x1 + +#define CUSTOM_SOV_OFFSET 4 +#define CUSTOM_SOV_MASK 0x7F +#define CUSTOM_EOV_OFFSET 5 +#define CUSTOM_EOV_MASK 0x80 + +#define IPV4_VER_OFFSET 0 +#define IPV4_VER_MATCH 0x4 +#define IPV4_VER_MASK 0xF +#define IPV6_VER_OFFSET 0 +#define IPV6_VER_MATCH 0x6 +#define IPV6_VER_MASK 0xF +#define CUSTOM_VER_OFFSET 0 +#define CUSTOM_VER_MATCH 0x2 +#define CUSTOM_VER_MASK 0xF + +static union nix_af_rx_flow_vec_ctrl0x nix_flow_ctrl0[NIX_AF_RX_FLOW_VEC_CTRL_MAX] = { + {.s.eov_inv = 0, + .s.eov_mask = 0, + .s.eov_offset = 0, + .s.sov_inv = 0, + .s.sov_mask = 0, + .s.sov_offset = 0, + .s.reserved = 0}, + {.s.eov_inv = 1, + .s.eov_mask = IPV4_EOV_MASK, + .s.eov_offset = IPV4_EOV_OFFSET, + .s.sov_inv = 1, + .s.sov_mask = IPV4_SOV_MASK, + .s.sov_offset = IPV4_SOV_OFFSET, + .s.reserved = 0}, + {.s.eov_inv = 1, + .s.eov_mask = IPV6_EOV_MASK, + .s.eov_offset = IPV6_EOV_OFFSET, + .s.sov_inv = 1, + .s.sov_mask = IPV6_SOV_MASK, + .s.sov_offset = IPV6_SOV_OFFSET, + .s.reserved = 0}, + {.s.eov_inv = 1, + .s.eov_mask = CUSTOM_EOV_MASK, + .s.eov_offset = CUSTOM_EOV_OFFSET, + .s.sov_inv = 1, + .s.sov_mask = CUSTOM_SOV_MASK, + .s.sov_offset = CUSTOM_SOV_OFFSET, + .s.reserved = 0}, +}; + +static union nix_af_rx_flow_vec_ctrl1x nix_flow_ctrl1[NIX_AF_RX_FLOW_VEC_CTRL_MAX] = { + {.s.ver_mask = 0, + .s.ver_match = 0, + .s.ver_offset = 0, + .s.ltype_mask = 0, + .s.ltype_match = 0, + .s.lid = 0, + .s.valid = 0, + .s.reserved = 0}, + {.s.ver_mask = IPV4_VER_MASK, + .s.ver_match = IPV4_VER_MATCH, + .s.ver_offset = IPV4_VER_OFFSET, + .s.ltype_mask = 0x3, + .s.ltype_match = NPC_LT_LC_IP, + .s.lid = NPC_LID_LC, + .s.valid = 1, + .s.reserved = 0}, + {.s.ver_mask = IPV6_VER_MASK, + .s.ver_match = IPV6_VER_MATCH, + .s.ver_offset = IPV6_VER_OFFSET, + .s.ltype_mask = 0x7, + .s.ltype_match = NPC_LT_LC_IP6, + .s.lid = NPC_LID_LC, + .s.valid = 1, + .s.reserved = 0}, + {.s.ver_mask = CUSTOM_VER_MASK, + .s.ver_match = CUSTOM_VER_MATCH, + .s.ver_offset = CUSTOM_VER_OFFSET, + .s.ltype_mask = 0xF, + .s.ltype_match = NPC_LT_LC_CUSTOM0, + .s.lid = NPC_LID_LC, + .s.valid = 1, + .s.reserved = 0}, +}; + +#endif /* _ROC_NIX_FLOW_VEC_H_ */ diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index 6a27f0e0fa..c7e7d2d8f6 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -95,6 +95,9 @@ #define NPC_CN20K_LFLAG_LC_OFFSET (NPC_LTYPE_OFFSET_START + 4) #define NPC_CN20K_LTYPE_LC_OFFSET (NPC_LTYPE_OFFSET_START + 5) +#define NPC_ACTION2_FLOW_VEC_VLD_FIELD 0xE +#define NPC_ACTION2_FLOW_VEC_FIELD 0xC + #define CN10K_SDP_CH_START 0x80 #define CN10K_SDP_CH_MASK 0xF80 diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c index 063cb21aae..00746abc06 100644 --- a/drivers/common/cnxk/roc_platform_base_symbols.c +++ b/drivers/common/cnxk/roc_platform_base_symbols.c @@ -96,6 +96,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_rvu_lf_free) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_mcs_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_mcs_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_mcs_free) +RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_af_rx_flow_vec_ctrl_set) RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_inl_outb_ring_base_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_nix_list_get) RTE_EXPORT_INTERNAL_SYMBOL(roc_idev_cpt_set) -- 2.43.0
