Introduce a generic Ethernet device API for cache stashing, supporting hardware mechanisms such as PCIe TPH (Transaction Processing Hints).
The API provides: - Generic query for supported stashing types and objects - Device-wide stashing enable/disable - Per-queue stashing with target lcore and data objects (Rx/Tx descriptor, header, payload) The design allows a device to support multiple stashing types while only allowing one active type at runtime. Signed-off-by: Chengwen Feng <[email protected]> --- lib/ethdev/ethdev_driver.h | 37 +++++++++++++++ lib/ethdev/rte_ethdev.c | 40 ++++++++++++++++ lib/ethdev/rte_ethdev.h | 95 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 1255cd6f2c..e7b4167939 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -1409,6 +1409,38 @@ enum rte_eth_dev_operation { typedef uint64_t (*eth_get_restore_flags_t)(struct rte_eth_dev *dev, enum rte_eth_dev_operation op); +/** + * @internal + * Get cache stash capabilities of the Ethernet device. + * + * @param dev + * Port (ethdev) handle. + * @param capa + * Pointer to capability structure to store supported stash types and objects. + * + * @return + * Negative on error, 0 on success. + */ +typedef int (*eth_cache_stash_get_t)(struct rte_eth_dev *dev, + struct rte_eth_cache_stash_capability *capa); + +/** + * @internal + * Configure cache stash for the Ethernet device or queue. + * + * @param dev + * Port (ethdev) handle. + * @param op + * Cache stash operation type (enable/disable device or queue). + * @param config + * Cache stash configuration (device or queue level). + * + * @return + * Negative on error, 0 on success. + */ +typedef int (*eth_cache_stash_set_t)(struct rte_eth_dev *dev, enum rte_eth_cache_stash_op op, + struct rte_eth_cache_stash_config *config); + /** * @internal A structure containing the functions exported by an Ethernet driver. */ @@ -1661,6 +1693,11 @@ struct eth_dev_ops { /** Get configuration which ethdev should restore */ eth_get_restore_flags_t get_restore_flags; + + /** Cache stash get ops */ + eth_cache_stash_get_t cache_stash_get; + /** Cache stash set ops */ + eth_cache_stash_set_t cache_stash_set; }; /** diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 2edc7a362e..4398aca5e1 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -7460,5 +7460,45 @@ int rte_eth_dev_map_aggr_tx_affinity(uint16_t port_id, uint16_t tx_queue_id, return ret; } +RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_eth_cache_stash_get, 26.03) +int +rte_eth_cache_stash_get(uint16_t port_id, + struct rte_eth_cache_stash_capability *capa) +{ + struct rte_eth_dev *dev; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + + if (capa == NULL) + return -EINVAL; + + dev = &rte_eth_devices[port_id]; + + if (*dev->dev_ops->cache_stash_get == NULL) + return -ENOTSUP; + + return eth_err(port_id, (*dev->dev_ops->cache_stash_get)(dev, capa)); +} + +RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_eth_cache_stash_set, 26.03) +int +rte_eth_cache_stash_set(uint16_t port_id, enum rte_eth_cache_stash_op op, + struct rte_eth_cache_stash_config *config) +{ + struct rte_eth_dev *dev; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + + if (op != RTE_ETH_CACHE_STASH_OP_DEV_DISABLE && config == NULL) + return -EINVAL; + + dev = &rte_eth_devices[port_id]; + + if (*dev->dev_ops->cache_stash_set == NULL) + return -ENOTSUP; + + return eth_err(port_id, (*dev->dev_ops->cache_stash_set)(dev, op, config)); +} + RTE_EXPORT_SYMBOL(rte_eth_dev_logtype) RTE_LOG_REGISTER_DEFAULT(rte_eth_dev_logtype, INFO); diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 0d8e2d0236..014f0c21b6 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -7178,6 +7178,101 @@ rte_eth_tx_queue_count(uint16_t port_id, uint16_t queue_id) return rc; } +/** + * Cache stash mechanisms (bitmask). + * A device may support multiple types but can only enable one at a time. + */ +enum rte_eth_cache_stash_type { + RTE_ETH_CACHE_STASH_TYPE_TPH = RTE_BIT32(0), +}; + +/** + * Cache stash objects (bitmask). + */ +#define RTE_ETH_CACHE_STASH_OBJ_RX_DESC RTE_BIT64(0) +#define RTE_ETH_CACHE_STASH_OBJ_TX_DESC RTE_BIT64(1) +#define RTE_ETH_CACHE_STASH_OBJ_RX_HEADER RTE_BIT64(2) +#define RTE_ETH_CACHE_STASH_OBJ_TX_HEADER RTE_BIT64(3) +#define RTE_ETH_CACHE_STASH_OBJ_RX_PAYLOAD RTE_BIT64(4) +#define RTE_ETH_CACHE_STASH_OBJ_TX_PAYLOAD RTE_BIT64(5) + +/** + * Cache stash capability. + */ +struct rte_eth_cache_stash_capability { + uint32_t supported_types; /**< Bitmask of rte_eth_cache_stash_type */ + uint64_t supported_objects;/**< Bitmask of RTE_ETH_CACHE_STASH_OBJ_* */ +}; + +/** + * Cache stash operations. + */ +enum rte_eth_cache_stash_op { + RTE_ETH_CACHE_STASH_OP_DEV_ENABLE, /**< Enable device-wide cache stash */ + RTE_ETH_CACHE_STASH_OP_DEV_DISABLE, /**< Disable device-wide cache stash */ + RTE_ETH_CACHE_STASH_OP_QUEUE_ENABLE, /**< Enable cache stash for a queue */ + RTE_ETH_CACHE_STASH_OP_QUEUE_DISABLE, /**< Disable cache stash for a queue */ + RTE_ETH_CACHE_STASH_OP_BUTT +}; + +/** + * Cache stash configuration. + * The used union member is determined by the operation. + */ +struct rte_eth_cache_stash_config { + union { + /** + * Device-level configuration (used with DEV_ENABLE). + */ + struct { + uint32_t type; /**< Selected stash mechanism type */ + } dev; + /** + * Queue-level configuration (used with QUEUE_ENABLE/QUEUE_DISABLE). + */ + struct { + uint32_t lcore_id; /**< Target CPU core ID */ + uint32_t queue_id; /**< Queue ID */ + uint64_t objects; /**< Objects bitmask to stash */ + } queue; + }; +}; + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Get cache stash capabilities of a port. + * + * @param port_id + * The port identifier. + * @param capa + * Output: supported stash types and objects. + * @return + * 0 on success, negative on error. + */ +__rte_experimental +int rte_eth_cache_stash_get(uint16_t port_id, struct rte_eth_cache_stash_capability *capa); + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Configure cache stash. + * + * @param port_id + * The port identifier. + * @param op + * Configuration operation. + * @param config + * Configuration structure. + * @return + * 0 on success, negative on error. + */ +__rte_experimental +int rte_eth_cache_stash_set(uint16_t port_id, enum rte_eth_cache_stash_op op, + struct rte_eth_cache_stash_config *config); + #ifdef __cplusplus } #endif -- 2.17.1
