From: Monendra Singh Kushwaha <kmonen...@marvell.com>
This patch enables setting CPT result address offset relative
to wqe address.
Signed-off-by: Monendra Singh Kushwaha <kmonen...@marvell.com>
---
Depends-on: series-34970 ("[v2,1/3] common/cnxk: update steer rule mbox for
cn20k")
drivers/common/cnxk/roc_mbox.h | 4 ++++
drivers/common/cnxk/roc_nix.c | 5 +++++
drivers/common/cnxk/roc_nix.h | 2 ++
drivers/common/cnxk/roc_nix_inl.c | 7 +++++++
drivers/common/cnxk/roc_nix_inl.h | 2 ++
drivers/common/cnxk/roc_nix_inl_dev.c | 7 +++++++
drivers/common/cnxk/roc_nix_inl_priv.h | 1 +
7 files changed, 28 insertions(+)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index a82d120d1d..255e0f0fe0 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2095,6 +2095,10 @@ struct nix_inline_ipsec_lf_cfg {
uint8_t __io sa_idx_w;
} ipsec_cfg1;
uint8_t __io enable;
+ struct {
+ uint8_t __io res_addr_offset;
+ uint8_t __io res_addr_offset_valid;
+ } ipsec_cfg0_ext;
};
struct nix_hw_info {
diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c
index e4d7e11121..477c7d5ca0 100644
--- a/drivers/common/cnxk/roc_nix.c
+++ b/drivers/common/cnxk/roc_nix.c
@@ -120,6 +120,11 @@ roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct
roc_nix_ipsec_cfg *cfg,
lf_cfg->ipsec_cfg0.sa_pow2_size = plt_log2_u32(cfg->sa_size);
lf_cfg->ipsec_cfg0.tag_const = cfg->tag_const;
lf_cfg->ipsec_cfg0.tt = cfg->tt;
+ if (cfg->res_addr_offset) {
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset_valid = 1;
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset =
+ (cfg->res_addr_offset & 0x80) |
abs(cfg->res_addr_offset);
+ }
} else {
lf_cfg->enable = 0;
}
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index a1bd14ffc4..80392e7e1b 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -431,6 +431,7 @@ struct roc_nix_ipsec_cfg {
plt_iova_t iova;
uint16_t max_sa;
uint8_t tt;
+ int8_t res_addr_offset;
};
/* Link status update callback */
@@ -469,6 +470,7 @@ struct roc_nix {
uint32_t dwrr_mtu;
bool ipsec_out_sso_pffunc;
bool custom_sa_action;
+ int8_t res_addr_offset;
bool local_meta_aura_ena;
uint32_t meta_buf_sz;
bool force_rx_aura_bp;
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 8ade58e1a2..6afdfb6b85 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -471,6 +471,11 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
lf_cfg->ipsec_cfg0.sa_pow2_size = sa_pow2_sz;
lf_cfg->ipsec_cfg0.tag_const = 0;
lf_cfg->ipsec_cfg0.tt = SSO_TT_ORDERED;
+ if (roc_nix->res_addr_offset) {
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset_valid = 1;
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset =
+ (roc_nix->res_addr_offset & 0x80) |
abs(roc_nix->res_addr_offset);
+ }
} else {
struct nix_rx_inl_lf_cfg_req *lf_cfg;
uint64_t def_cptq = 0;
@@ -2155,6 +2160,8 @@ roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix,
uint32_t tag_const,
cfg.max_sa = nix->inb_spi_mask + 1;
cfg.tt = tt;
cfg.tag_const = tag_const;
+ if (roc_nix->res_addr_offset)
+ cfg.res_addr_offset = roc_nix->res_addr_offset;
return roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
}
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index dab4918535..4ef1908696 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -99,6 +99,8 @@ struct roc_nix_inl_dev {
uint8_t rx_inj_ena; /* Rx Inject Enable */
uint8_t custom_inb_sa;
uint8_t nb_inb_cptlfs;
+ int8_t res_addr_offset; /* CPT result address offset */
+
/* End of input parameters */
#define ROC_NIX_INL_MEM_SZ (6144)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 376582f5db..1db05741ad 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -365,6 +365,12 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool
ena)
lf_cfg->ipsec_cfg0.tag_const = 0;
lf_cfg->ipsec_cfg0.tt = SSO_TT_ORDERED;
+ if (inl_dev->res_addr_offset) {
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset_valid =
1;
+ lf_cfg->ipsec_cfg0_ext.res_addr_offset =
+ (inl_dev->res_addr_offset & 0x80) |
+ abs(inl_dev->res_addr_offset);
+ }
} else {
lf_cfg->enable = 0;
}
@@ -1370,6 +1376,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
inl_dev->nix_inb_q_bpid = -1;
inl_dev->nb_cptlf = 1;
inl_dev->ipsec_prof_id = 0;
+ inl_dev->res_addr_offset = roc_inl_dev->res_addr_offset;
if (roc_model_is_cn9k() || roc_model_is_cn10k())
inl_dev->eng_grpmask = (1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE |
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h
b/drivers/common/cnxk/roc_nix_inl_priv.h
index 8b3bd43547..33073b2f34 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -67,6 +67,7 @@ struct nix_inl_dev {
uint16_t inb_sa_sz[NIX_INL_PROFILE_CNT];
uint32_t inb_sa_max[NIX_INL_PROFILE_CNT];
uint8_t nb_cptlf;
+ int8_t res_addr_offset;
/* CPT data */
struct roc_cpt_lf cpt_lf[MAX_NIX_INL_DEV_CPT_LF];
--
2.25.1
