On Tue, Apr 2, 2024 at 2:46 AM Stephen Hemminger <step...@networkplumber.org> wrote: > > On Mon, 1 Apr 2024 18:26:44 -0400 > Patrick Robb <pr...@iol.unh.edu> wrote: > > > Another idea - maybe multiple timestamps are gathered from different > > CPU registers during the same test, and they are misaligned for that > > reason. Maybe we can try reducing the cores for each unit test to 1 > > and checking whether the issue persists. > > TSC is expected to be sync'd between cores. But of course packets can > arrive out of order on different cores.
Just a note that there was one more occurence of this false positive today. https://lab.dpdk.org/results/dashboard/patchsets/33170/ -- David Marchand
