PMD statically assumed that REG_C_6 is always available for use
with NAT64 HW flow action.
This led to PMD configuration errors on FW versions which do not expose
that specific register.
This patch fixes that by adding a check for REG_C_6 against FW
capabilities, when registers for NAT64 are selected.
Also, if not enough registers are available, PMD will not attempt to
create NAT64 actions.
Fixes: 7a26bfec06a4 ("net/mlx5: fetch available registers for NAT64")
Cc: sta...@dpdk.org
Signed-off-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
Acked-by: Bing Zhao <bi...@nvidia.com>
---
drivers/net/mlx5/mlx5.c | 16 +++++++++++-----
drivers/net/mlx5/mlx5_flow_hw.c | 22 ++++++++++++++++++++--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 0f49cb5e5b..e175f81031 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1624,7 +1624,8 @@ mlx5_init_hws_flow_tags_registers(struct
mlx5_dev_ctx_shared *sh)
{
struct mlx5_dev_registers *reg = &sh->registers;
uint32_t meta_mode = sh->config.dv_xmeta_en;
- uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;
+ uint16_t reg_c_caps = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;
+ uint16_t masks = reg_c_caps;
uint16_t unset = 0;
uint32_t i, j;
@@ -1648,11 +1649,16 @@ mlx5_init_hws_flow_tags_registers(struct
mlx5_dev_ctx_shared *sh)
* Set the registers for NAT64 usage internally. REG_C_6 is always used.
* The other 2 registers will be fetched from right to left, at least 2
* tag registers should be available.
+ * If not enough registers are available or REG_C_6 is not supported by
current FW,
+ * NAT64 action will not be supported.
*/
- MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1));
- reg->nat64_regs[0] = REG_C_6;
- reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
- reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+ if ((reg_c_caps & RTE_BIT32(mlx5_regc_index(REG_C_6))) &&
+ j >= MLX5_FLOW_NAT64_REGS_MAX - 1) {
+ MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1));
+ reg->nat64_regs[0] = REG_C_6;
+ reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
+ reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+ }
}
static void
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 6254857301..20d38ce414 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -9656,6 +9656,19 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv
*priv)
}
}
+static bool
+flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
+{
+ int i;
+
+ /* Check if all registers are available. */
+ for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
+ if (priv->sh->registers.nat64_regs[i] == REG_NON)
+ return false;
+
+ return true;
+}
+
static void
flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
{
@@ -12197,9 +12210,14 @@ __flow_hw_configure(struct rte_eth_dev *dev,
NULL, "Failed to VLAN actions.");
goto err;
}
- if (flow_hw_create_nat64_actions(priv, error))
+ if (flow_hw_should_create_nat64_actions(priv)) {
+ if (flow_hw_create_nat64_actions(priv, error))
+ goto err;
+ } else {
DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
- "please check the FW version", dev->data->port_id);
+ "please check the FW version. NAT64 will not be
supported.",
+ dev->data->port_id);
+ }
if (_queue_attr)
mlx5_free(_queue_attr);
if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)
--
2.39.5
