On Fri, 21 Feb 2025 16:54:40 +0000
Chris MacNamara <chris.macnam...@intel.com> wrote:

> A recent CPU change requires an extra enabling step for
> the umonitor instruction on Intel CPUs.
> This is now detailed in the l3 fwd power manager doc.
> 
> Signed-off-by: Chris MacNamara <chris.macnam...@intel.com>
> ---
>  .mailmap                                          | 1 +
>  doc/guides/sample_app_ug/l3_forward_power_man.rst | 5 +++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/.mailmap b/.mailmap
> index a03d3cfb59..c4bc38752f 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -263,6 +263,7 @@ Christopher Reder <christopher.re...@broadcom.com>
>  Christoph Gysin <christoph.gy...@gmail.com>
>  Christos Ricudis <ricu...@niometrics.com>
>  Chris Wright <chr...@redhat.com>
> +Chris MacNamara <chris.macnam...@intel.com>
>  Chuanshe Zhang <zhangchuan...@icloudshield.com>
>  Chuanyu Xue <chuanyu....@uconn.edu>
>  Chuhong Yao <y...@panath.cn>
> diff --git a/doc/guides/sample_app_ug/l3_forward_power_man.rst 
> b/doc/guides/sample_app_ug/l3_forward_power_man.rst
> index 3271bc2154..d0af28e0ec 100644
> --- a/doc/guides/sample_app_ug/l3_forward_power_man.rst
> +++ b/doc/guides/sample_app_ug/l3_forward_power_man.rst
> @@ -293,6 +293,11 @@ and has three available power management schemes:
>  ``monitor``
>    This will use ``rte_power_monitor()`` function to enter
>    a power-optimized state (subject to platform support).
> +  On recent Gen 4 Xeon Scalable Processors the umonitor instruction
> +  is disabled by default.
> +  An additional step is required to enable the umonitor instruction.
> +  Writing 0 to bit 6 of register 0x123 will enable umonitor.
> +  `More details are available via Monitor and Umonitor Performance Guidance 
> <https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html>`_
>  

This should be done by the power library, what is the point of having a power 
API
if we require applications to test for CPU type and go tweak some CPU register 
bits.
And it may be restricted by OS permissions etc.

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