Some definitions that are present in the base code are missing from DPDK. This patch adds the following definitions:
- EEPROM R/W v2 modes - BAR ctrl CSR shift size - I225 flash access register - EEE-related registers Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com> --- drivers/net/intel/e1000/base/e1000_defines.h | 5 +++++ drivers/net/intel/e1000/base/e1000_regs.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h index d795c327a3..3d3bc3f6dc 100644 --- a/drivers/net/intel/e1000/base/e1000_defines.h +++ b/drivers/net/intel/e1000/base/e1000_defines.h @@ -947,6 +947,11 @@ #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ #define E1000_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */ #define E1000_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */ +#define E1000_EEE_LP_ADV_2_5G 0 /* EEE LP Adv 2.5G */ +#define E1000_EEE_LP_ADV_1G 2 /* EEE LP Adv 1G */ +#define E1000_EEE_LP_ADV_100M 1 /* EEE LP Adv 100M */ +#define E1000_ANEG_EEE_AN_LPAB1_I225 26 /* EEE LP Ability 1 Offset */ +#define E1000_ANEG_EEE_AN_LPAB2_I225 0x2A /* EEE LP Ability 2 Offset */ /* PCI Express Control */ #define E1000_GCR_RXD_NO_SNOOP 0x00000001 diff --git a/drivers/net/intel/e1000/base/e1000_regs.h b/drivers/net/intel/e1000/base/e1000_regs.h index 994e3c391b..3af356be77 100644 --- a/drivers/net/intel/e1000/base/e1000_regs.h +++ b/drivers/net/intel/e1000/base/e1000_regs.h @@ -12,6 +12,8 @@ #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ #define E1000_EERD 0x00014 /* EEPROM Read - RW */ #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define E1000_EERD_V2 0x12014 /* EEprom mode read - RW */ +#define E1000_EEWR_V2 0x12018 /* EEprom mode write - RW */ /* NVM Register Descriptions */ #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ #define E1000_FLA 0x0001C /* Flash Access - RW */ @@ -23,6 +25,7 @@ #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ +#define E1000_BARCTRL_CSRSIZE_SHIFT 13 #define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ #define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */ #define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ @@ -33,6 +36,7 @@ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ #define E1000_FEXT 0x0002C /* Future Extended - RW */ +#define E1000_I225_FLA 0x1201C /* FLASH access register */ #define E1000_I225_FLSWCTL 0x12048 /* FLASH control register */ #define E1000_I225_FLSWDATA 0x1204C /* FLASH data register */ #define E1000_I225_FLSWCNT 0x12050 /* FLASH Access Counter */ -- 2.43.5
