The dqrr_held mask is 64 bit but updates were getting truncated because 1 is of type int (32 bit) and the result shift of int is of type int (32 bit); therefore any value >= 32 would get truncated.
Link: https://pvs-studio.com/en/blog/posts/cpp/1183/ Fixes: a77db24643b7 ("crypto/dpaa2_sec: support atomic queues") Cc: ashish.j...@nxp.com Cc: sta...@dpdk.org Signed-off-by: Stephen Hemminger <step...@networkplumber.org> Acked-by: Hemant Agrawal <hemant.agra...@nxp.com> --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index ec6577f64c..7ad8fd47dd 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -1491,8 +1491,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, if (*dpaa2_seqn((*ops)->sym->m_src)) { if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) { DPAA2_PER_LCORE_DQRR_SIZE--; - DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << - *dpaa2_seqn((*ops)->sym->m_src) & + DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << + *dpaa2_seqn((*ops)->sym->m_src) & QBMAN_EQCR_DCA_IDXMASK); } flags[loop] = *dpaa2_seqn((*ops)->sym->m_src); @@ -1772,7 +1772,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q, dq_idx = *dpaa2_seqn(m) - 1; qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0); DPAA2_PER_LCORE_DQRR_SIZE--; - DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx); + DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx); } *dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN; } @@ -4055,7 +4055,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused, dqrr_index = qbman_get_dqrr_idx(dq); *dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index; DPAA2_PER_LCORE_DQRR_SIZE++; - DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index; + DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index; DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src; ev->event_ptr = crypto_op; } -- 2.45.2
