On Wed, Aug 21, 2024 at 2:43 PM Nicholas Pratte <npra...@iol.unh.edu> wrote:
> The current design requires that a peer pci port is identified so that > test suites can create the correct port links. While this can work, it > also creates a lot of room for user error. Instead, devices should be > given a unique identifier which is referenced in defined test runs. > > Both defined testbeds for the SUT and TG must have an equal number of > specified ports. In each given array or ports, SUT port 0 is connected > to TG port 0, SUT port 1 is connected to TG port 1, etc. > > Bugzilla ID: 1478 > > Signed-off-by: Nicholas Pratte <npra...@iol.unh.edu> > Aside from Jeremy/Juraj's comments and assuming this will get extended off the pydantic series: Reviewed-by: Dean Marx <dm...@iol.unh.edu>
