From: Pavan Nikhilesh <pbhagavat...@marvell.com>
Add platform specific event device probe and remove, also add
event device info get function.
Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
---
doc/guides/eventdevs/cnxk.rst | 23 ++++---
doc/guides/rel_notes/release_24_11.rst | 4 ++
drivers/common/cnxk/roc_sso.c | 10 ++-
drivers/event/cnxk/cn20k_eventdev.c | 93 ++++++++++++++++++++++++++
drivers/event/cnxk/meson.build | 8 ++-
5 files changed, 124 insertions(+), 14 deletions(-)
create mode 100644 drivers/event/cnxk/cn20k_eventdev.c
diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst
index e21846f4e0..55028f889b 100644
--- a/doc/guides/eventdevs/cnxk.rst
+++ b/doc/guides/eventdevs/cnxk.rst
@@ -16,6 +16,7 @@ Supported OCTEON cnxk SoCs
- CN9XX
- CN10XX
+- CN20XX
Features
--------
@@ -36,7 +37,7 @@ Features of the OCTEON cnxk SSO PMD are:
DRAM
- HW accelerated dequeue timeout support to enable power management
- HW managed event timers support through TIM, with high precision and
- time granularity of 2.5us on CN9K and 1us on CN10K.
+ time granularity of 2.5us on CN9K and 1us on CN10K/CN20K.
- Up to 256 TIM rings a.k.a event timer adapters.
- Up to 8 rings traversed in parallel.
- HW managed packets enqueued from ethdev to eventdev exposed through event eth
@@ -45,8 +46,8 @@ Features of the OCTEON cnxk SSO PMD are:
- Lockfree Tx from event eth Tx adapter using
``RTE_ETH_TX_OFFLOAD_MT_LOCKFREE``
capability while maintaining receive packet order.
- Full Rx/Tx offload support defined through ethdev queue configuration.
-- HW managed event vectorization on CN10K for packets enqueued from ethdev to
- eventdev configurable per each Rx queue in Rx adapter.
+- HW managed event vectorization on CN10K/CN20K for packets enqueued from
ethdev
+ to eventdev configurable per each Rx queue in Rx adapter.
- Event vector transmission via Tx adapter.
- Up to 2 event link profiles.
@@ -93,13 +94,13 @@ Runtime Config Options
-a 0002:0e:00.0,qos=[1-50-50]
-- ``CN10K WQE stashing support``
+- ``CN10K/CN20K WQE stashing support``
- CN10K supports stashing the scheduled WQE carried by `rte_event` to the
- cores L2 Dcache. The number of cache lines to be stashed and the offset
- is configurable per HWGRP i.e. event queue. The dictionary format is as
- follows `[Qx|stash_offset|stash_length]` here the stash offset can be
- a negative integer.
+ CN10K/CN20K supports stashing the scheduled WQE carried by `rte_event`
+ to the cores L2 Dcache. The number of cache lines to be stashed and the
+ offset is configurable per HWGRP i.e. event queue. The dictionary format
+ is as follows `[Qx|stash_offset|stash_length]` here the stash offset can
+ be a negative integer.
By default, stashing is enabled on queues which have been connected to
Rx adapter. Both MBUF and NIX_RX_WQE_HDR + NIX_RX_PARSE_S are stashed.
@@ -188,8 +189,8 @@ Runtime Config Options
-a 0002:0e:00.0,tim_eclk_freq=122880000-1000000000-0
-Power Saving on CN10K
----------------------
+Power Saving on CN10K/CN20K
+---------------------------
ARM cores can additionally use WFE when polling for transactions on SSO bus
to save power i.e., in the event dequeue call ARM core can enter WFE and exit
diff --git a/doc/guides/rel_notes/release_24_11.rst
b/doc/guides/rel_notes/release_24_11.rst
index 5461798970..680d7a0199 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -231,6 +231,10 @@ New Features
* Added independent enqueue feature.
+* **Updated Marvell cnxk event device driver.**
+
+ * Added eventdev driver support for CN20K SoC.
+
* **Added IPv4 network order lookup in the FIB library.**
A new flag field is introduced in ``rte_fib_conf`` structure.
diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c
index 8a219b985b..45cf6fc39e 100644
--- a/drivers/common/cnxk/roc_sso.c
+++ b/drivers/common/cnxk/roc_sso.c
@@ -870,7 +870,10 @@ sso_update_msix_vec_count(struct roc_sso *roc_sso,
uint16_t sso_vec_cnt)
if (idev == NULL)
return -ENODEV;
- mbox_vec_cnt = RVU_PF_INT_VEC_AFPF_MBOX + 1;
+ if (roc_model_is_cn20k())
+ mbox_vec_cnt = RVU_MBOX_PF_INT_VEC_AFPF_MBOX + 1;
+ else
+ mbox_vec_cnt = RVU_PF_INT_VEC_AFPF_MBOX + 1;
/* Allocating vectors for the first time */
if (plt_intr_max_intr_get(pci_dev->intr_handle) == 0) {
@@ -1017,7 +1020,10 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t
nb_hws, uint16_t nb_hwgrp, ui
}
/* 2 error interrupt per TIM LF */
- sso_vec_cnt += 2 * nb_tim_lfs;
+ if (roc_model_is_cn20k())
+ sso_vec_cnt += 3 * nb_tim_lfs;
+ else
+ sso_vec_cnt += 2 * nb_tim_lfs;
rc = sso_update_msix_vec_count(roc_sso, sso_vec_cnt);
if (rc < 0) {
diff --git a/drivers/event/cnxk/cn20k_eventdev.c
b/drivers/event/cnxk/cn20k_eventdev.c
new file mode 100644
index 0000000000..c4b80f64f3
--- /dev/null
+++ b/drivers/event/cnxk/cn20k_eventdev.c
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#include "roc_api.h"
+
+#include "cnxk_eventdev.h"
+
+static void
+cn20k_sso_set_rsrc(void *arg)
+{
+ struct cnxk_sso_evdev *dev = arg;
+
+ dev->max_event_ports = dev->sso.max_hws;
+ dev->max_event_queues = dev->sso.max_hwgrp >
RTE_EVENT_MAX_QUEUES_PER_DEV ?
+ RTE_EVENT_MAX_QUEUES_PER_DEV :
+ dev->sso.max_hwgrp;
+}
+
+static void
+cn20k_sso_info_get(struct rte_eventdev *event_dev, struct rte_event_dev_info
*dev_info)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+
+ dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN20K_PMD);
+ cnxk_sso_info_get(dev, dev_info);
+ dev_info->max_event_port_enqueue_depth = UINT32_MAX;
+}
+
+static struct eventdev_ops cn20k_sso_dev_ops = {
+ .dev_infos_get = cn20k_sso_info_get,
+};
+
+static int
+cn20k_sso_init(struct rte_eventdev *event_dev)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ int rc;
+
+ rc = roc_plt_init();
+ if (rc < 0) {
+ plt_err("Failed to initialize platform model");
+ return rc;
+ }
+
+ event_dev->dev_ops = &cn20k_sso_dev_ops;
+ /* For secondary processes, the primary has done all the work */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ rc = cnxk_sso_init(event_dev);
+ if (rc < 0)
+ return rc;
+
+ cn20k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
+ if (!dev->max_event_ports || !dev->max_event_queues) {
+ plt_err("Not enough eventdev resource queues=%d ports=%d",
dev->max_event_queues,
+ dev->max_event_ports);
+ cnxk_sso_fini(event_dev);
+ return -ENODEV;
+ }
+
+ plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
event_dev->data->name,
+ dev->max_event_queues, dev->max_event_ports);
+
+ return 0;
+}
+
+static int
+cn20k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
+{
+ return rte_event_pmd_pci_probe(pci_drv, pci_dev, sizeof(struct
cnxk_sso_evdev),
+ cn20k_sso_init);
+}
+
+static const struct rte_pci_id cn20k_pci_sso_map[] = {
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN20KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN20KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cn20k_pci_sso = {
+ .id_table = cn20k_pci_sso_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+ .probe = cn20k_sso_probe,
+ .remove = cnxk_sso_remove,
+};
+
+RTE_PMD_REGISTER_PCI(event_cn20k, cn20k_pci_sso);
+RTE_PMD_REGISTER_PCI_TABLE(event_cn20k, cn20k_pci_sso_map);
+RTE_PMD_REGISTER_KMOD_DEP(event_cn20k, "vfio-pci");
diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build
index 6757af74bf..21cd5c5ae6 100644
--- a/drivers/event/cnxk/meson.build
+++ b/drivers/event/cnxk/meson.build
@@ -14,7 +14,7 @@ else
soc_type = platform
endif
-if soc_type != 'cn9k' and soc_type != 'cn10k'
+if soc_type != 'cn9k' and soc_type != 'cn10k' and soc_type != 'cn20k'
soc_type = 'all'
endif
@@ -229,6 +229,12 @@ sources += files(
endif
endif
+if soc_type == 'cn20k' or soc_type == 'all'
+sources += files(
+ 'cn20k_eventdev.c',
+)
+endif
+
extra_flags = ['-flax-vector-conversions', '-Wno-strict-aliasing']
if cc.get_id() == 'clang'
extra_flags += ['-Wno-asm-operand-widths']
--
2.25.1
