From: Danylo Vodopianov <dvo-...@napatech.com>
The Receive Port FIFO module controls the small FPGA FIFO
that packets are stored in before they enter the packet processor pipeline.
Signed-off-by: Danylo Vodopianov <dvo-...@napatech.com>
---
.../net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c | 25 +++-
drivers/net/ntnic/include/ntnic_stat.h | 2 +
drivers/net/ntnic/meson.build | 1 +
.../net/ntnic/nthw/core/include/nthw_rpf.h | 48 +++++++
drivers/net/ntnic/nthw/core/nthw_rpf.c | 119 ++++++++++++++++++
.../net/ntnic/nthw/model/nthw_fpga_model.c | 12 ++
.../net/ntnic/nthw/model/nthw_fpga_model.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 +
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 +
.../nthw/supported/nthw_fpga_reg_defs_rpf.h | 19 +++
10 files changed, 228 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_rpf.h
create mode 100644 drivers/net/ntnic/nthw/core/nthw_rpf.c
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
diff --git a/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c
b/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c
index 0e20f3ea45..f733fd5459 100644
--- a/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c
+++ b/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c
@@ -11,6 +11,7 @@
#include "nt4ga_adapter.h"
#include "ntnic_nim.h"
#include "flow_filter.h"
+#include "ntnic_stat.h"
#include "ntnic_mod_reg.h"
#define DEFAULT_MAX_BPS_SPEED 100e9
@@ -43,7 +44,7 @@ static int nt4ga_stat_init(struct adapter_info_s
*p_adapter_info)
if (!p_nthw_rmc) {
nthw_stat_delete(p_nthw_stat);
- NT_LOG(ERR, NTNIC, "%s: ERROR ",
p_adapter_id_str);
+ NT_LOG(ERR, NTNIC, "%s: ERROR rmc allocation",
p_adapter_id_str);
return -1;
}
@@ -54,6 +55,22 @@ static int nt4ga_stat_init(struct adapter_info_s
*p_adapter_info)
p_nt4ga_stat->mp_nthw_rmc = NULL;
}
+ if (nthw_rpf_init(NULL, p_fpga, p_adapter_info->adapter_no) ==
0) {
+ nthw_rpf_t *p_nthw_rpf = nthw_rpf_new();
+
+ if (!p_nthw_rpf) {
+ nthw_stat_delete(p_nthw_stat);
+ NT_LOG_DBGX(ERR, NTNIC, "%s: ERROR",
p_adapter_id_str);
+ return -1;
+ }
+
+ nthw_rpf_init(p_nthw_rpf, p_fpga,
p_adapter_info->adapter_no);
+ p_nt4ga_stat->mp_nthw_rpf = p_nthw_rpf;
+
+ } else {
+ p_nt4ga_stat->mp_nthw_rpf = NULL;
+ }
+
p_nt4ga_stat->mp_nthw_stat = p_nthw_stat;
nthw_stat_init(p_nthw_stat, p_fpga, 0);
@@ -77,6 +94,9 @@ static int nt4ga_stat_setup(struct adapter_info_s
*p_adapter_info)
if (p_nt4ga_stat->mp_nthw_rmc)
nthw_rmc_block(p_nt4ga_stat->mp_nthw_rmc);
+ if (p_nt4ga_stat->mp_nthw_rpf)
+ nthw_rpf_block(p_nt4ga_stat->mp_nthw_rpf);
+
/* Allocate and map memory for fpga statistics */
{
uint32_t n_stat_size = (uint32_t)(p_nthw_stat->m_nb_counters *
sizeof(uint32_t) +
@@ -112,6 +132,9 @@ static int nt4ga_stat_setup(struct adapter_info_s
*p_adapter_info)
if (p_nt4ga_stat->mp_nthw_rmc)
nthw_rmc_unblock(p_nt4ga_stat->mp_nthw_rmc, false);
+ if (p_nt4ga_stat->mp_nthw_rpf)
+ nthw_rpf_unblock(p_nt4ga_stat->mp_nthw_rpf);
+
p_nt4ga_stat->mp_stat_structs_color =
calloc(p_nthw_stat->m_nb_color_counters, sizeof(struct
color_counters));
diff --git a/drivers/net/ntnic/include/ntnic_stat.h
b/drivers/net/ntnic/include/ntnic_stat.h
index 2aee3f8425..ed24a892ec 100644
--- a/drivers/net/ntnic/include/ntnic_stat.h
+++ b/drivers/net/ntnic/include/ntnic_stat.h
@@ -8,6 +8,7 @@
#include "common_adapter_defs.h"
#include "nthw_rmc.h"
+#include "nthw_rpf.h"
#include "nthw_fpga_model.h"
#define NT_MAX_COLOR_FLOW_STATS 0x400
@@ -102,6 +103,7 @@ struct flm_counters_v1 {
struct nt4ga_stat_s {
nthw_stat_t *mp_nthw_stat;
nthw_rmc_t *mp_nthw_rmc;
+ nthw_rpf_t *mp_nthw_rpf;
struct nt_dma_s *p_stat_dma;
uint32_t *p_stat_dma_virtual;
uint32_t n_stat_size;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 216341bb11..ed5a201fd5 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -47,6 +47,7 @@ sources = files(
'nthw/core/nthw_iic.c',
'nthw/core/nthw_mac_pcs.c',
'nthw/core/nthw_pcie3.c',
+ 'nthw/core/nthw_rpf.c',
'nthw/core/nthw_rmc.c',
'nthw/core/nthw_sdc.c',
'nthw/core/nthw_si5340.c',
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_rpf.h
b/drivers/net/ntnic/nthw/core/include/nthw_rpf.h
new file mode 100644
index 0000000000..4c6c57ba55
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_rpf.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_RPF_HPP_
+#define NTHW_RPF_HPP_
+
+#include "nthw_fpga_model.h"
+#include "pthread.h"
+struct nthw_rpf {
+ nthw_fpga_t *mp_fpga;
+
+ nthw_module_t *m_mod_rpf;
+
+ int mn_instance;
+
+ nthw_register_t *mp_reg_control;
+ nthw_field_t *mp_fld_control_pen;
+ nthw_field_t *mp_fld_control_rpp_en;
+ nthw_field_t *mp_fld_control_st_tgl_en;
+ nthw_field_t *mp_fld_control_keep_alive_en;
+
+ nthw_register_t *mp_ts_sort_prg;
+ nthw_field_t *mp_fld_ts_sort_prg_maturing_delay;
+ nthw_field_t *mp_fld_ts_sort_prg_ts_at_eof;
+
+ int m_default_maturing_delay;
+ bool m_administrative_block; /* used to enforce license expiry */
+
+ pthread_mutex_t rpf_mutex;
+};
+
+typedef struct nthw_rpf nthw_rpf_t;
+typedef struct nthw_rpf nt_rpf;
+
+nthw_rpf_t *nthw_rpf_new(void);
+void nthw_rpf_delete(nthw_rpf_t *p);
+int nthw_rpf_init(nthw_rpf_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_rpf_administrative_block(nthw_rpf_t *p);
+void nthw_rpf_block(nthw_rpf_t *p);
+void nthw_rpf_unblock(nthw_rpf_t *p);
+void nthw_rpf_set_maturing_delay(nthw_rpf_t *p, int32_t delay);
+int32_t nthw_rpf_get_maturing_delay(nthw_rpf_t *p);
+void nthw_rpf_set_ts_at_eof(nthw_rpf_t *p, bool enable);
+bool nthw_rpf_get_ts_at_eof(nthw_rpf_t *p);
+
+#endif
diff --git a/drivers/net/ntnic/nthw/core/nthw_rpf.c
b/drivers/net/ntnic/nthw/core/nthw_rpf.c
new file mode 100644
index 0000000000..81c704d01a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_rpf.c
@@ -0,0 +1,119 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_rpf.h"
+
+nthw_rpf_t *nthw_rpf_new(void)
+{
+ nthw_rpf_t *p = malloc(sizeof(nthw_rpf_t));
+
+ if (p)
+ memset(p, 0, sizeof(nthw_rpf_t));
+
+ return p;
+}
+
+void nthw_rpf_delete(nthw_rpf_t *p)
+{
+ if (p) {
+ memset(p, 0, sizeof(nthw_rpf_t));
+ free(p);
+ }
+}
+
+int nthw_rpf_init(nthw_rpf_t *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+ nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_RPF,
n_instance);
+
+ if (p == NULL)
+ return p_mod == NULL ? -1 : 0;
+
+ if (p_mod == NULL) {
+ NT_LOG(ERR, NTHW, "%s: MOD_RPF %d: no such instance",
+ p->mp_fpga->p_fpga_info->mp_adapter_id_str,
p->mn_instance);
+ return -1;
+ }
+
+ p->m_mod_rpf = p_mod;
+
+ p->mp_fpga = p_fpga;
+
+ p->m_administrative_block = false;
+
+ /* CONTROL */
+ p->mp_reg_control = nthw_module_get_register(p->m_mod_rpf, RPF_CONTROL);
+ p->mp_fld_control_pen = nthw_register_get_field(p->mp_reg_control,
RPF_CONTROL_PEN);
+ p->mp_fld_control_rpp_en = nthw_register_get_field(p->mp_reg_control,
RPF_CONTROL_RPP_EN);
+ p->mp_fld_control_st_tgl_en =
+ nthw_register_get_field(p->mp_reg_control,
RPF_CONTROL_ST_TGL_EN);
+ p->mp_fld_control_keep_alive_en =
+ nthw_register_get_field(p->mp_reg_control,
RPF_CONTROL_KEEP_ALIVE_EN);
+
+ /* TS_SORT_PRG */
+ p->mp_ts_sort_prg = nthw_module_get_register(p->m_mod_rpf,
RPF_TS_SORT_PRG);
+ p->mp_fld_ts_sort_prg_maturing_delay =
+ nthw_register_get_field(p->mp_ts_sort_prg,
RPF_TS_SORT_PRG_MATURING_DELAY);
+ p->mp_fld_ts_sort_prg_ts_at_eof =
+ nthw_register_get_field(p->mp_ts_sort_prg,
RPF_TS_SORT_PRG_TS_AT_EOF);
+ p->m_default_maturing_delay =
+ nthw_fpga_get_product_param(p_fpga,
NT_RPF_MATURING_DEL_DEFAULT, 0);
+
+ /* Initialize mutex */
+ pthread_mutex_init(&p->rpf_mutex, NULL);
+ return 0;
+}
+
+void nthw_rpf_administrative_block(nthw_rpf_t *p)
+{
+ /* block all MAC ports */
+ nthw_register_update(p->mp_reg_control);
+ nthw_field_set_val_flush32(p->mp_fld_control_pen, 0);
+
+ p->m_administrative_block = true;
+}
+
+void nthw_rpf_block(nthw_rpf_t *p)
+{
+ nthw_register_update(p->mp_reg_control);
+ nthw_field_set_val_flush32(p->mp_fld_control_pen, 0);
+}
+
+void nthw_rpf_unblock(nthw_rpf_t *p)
+{
+ nthw_register_update(p->mp_reg_control);
+
+ nthw_field_set_val32(p->mp_fld_control_pen, ~0U);
+ nthw_field_set_val32(p->mp_fld_control_rpp_en, ~0U);
+ nthw_field_set_val32(p->mp_fld_control_st_tgl_en, 1);
+ nthw_field_set_val_flush32(p->mp_fld_control_keep_alive_en, 1);
+}
+
+void nthw_rpf_set_maturing_delay(nthw_rpf_t *p, int32_t delay)
+{
+ nthw_register_update(p->mp_ts_sort_prg);
+ nthw_field_set_val_flush32(p->mp_fld_ts_sort_prg_maturing_delay,
(uint32_t)delay);
+}
+
+int32_t nthw_rpf_get_maturing_delay(nthw_rpf_t *p)
+{
+ nthw_register_update(p->mp_ts_sort_prg);
+ /* Maturing delay is a two's complement 18 bit value, so we retrieve it
as signed */
+ return nthw_field_get_signed(p->mp_fld_ts_sort_prg_maturing_delay);
+}
+
+void nthw_rpf_set_ts_at_eof(nthw_rpf_t *p, bool enable)
+{
+ nthw_register_update(p->mp_ts_sort_prg);
+ nthw_field_set_val_flush32(p->mp_fld_ts_sort_prg_ts_at_eof, enable);
+}
+
+bool nthw_rpf_get_ts_at_eof(nthw_rpf_t *p)
+{
+ return nthw_field_get_updated(p->mp_fld_ts_sort_prg_ts_at_eof);
+}
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
index 4d495f5b96..9eaaeb550d 100644
--- a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
@@ -1050,6 +1050,18 @@ uint32_t nthw_field_get_val32(const nthw_field_t *p)
return val;
}
+int32_t nthw_field_get_signed(const nthw_field_t *p)
+{
+ uint32_t val;
+
+ nthw_field_get_val(p, &val, 1);
+
+ if (val & (1U << nthw_field_get_bit_pos_high(p))) /* check sign */
+ val = val | ~nthw_field_get_mask(p); /* sign extension */
+
+ return (int32_t)val; /* cast to signed value */
+}
+
uint32_t nthw_field_get_updated(const nthw_field_t *p)
{
uint32_t val;
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
index 7956f0689e..d4e7ab3edd 100644
--- a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
@@ -227,6 +227,7 @@ void nthw_field_get_val(const nthw_field_t *p, uint32_t
*p_data, uint32_t len);
void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data,
uint32_t len);
void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data,
uint32_t len);
uint32_t nthw_field_get_val32(const nthw_field_t *p);
+int32_t nthw_field_get_signed(const nthw_field_t *p);
uint32_t nthw_field_get_updated(const nthw_field_t *p);
void nthw_field_update_register(const nthw_field_t *p);
void nthw_field_flush_register(const nthw_field_t *p);
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index ddc144dc02..03122acaf5 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -41,6 +41,7 @@
#define MOD_RAC (0xae830b42UL)
#define MOD_RMC (0x236444eUL)
#define MOD_RPL (0x6de535c3UL)
+#define MOD_RPF (0x8d30dcddUL)
#define MOD_RPP_LR (0xba7f945cUL)
#define MOD_RST9563 (0x385d6d1dUL)
#define MOD_SDC (0xd2369530UL)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index 8f196f885f..7067f4b1d0 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -39,6 +39,7 @@
#include "nthw_fpga_reg_defs_qsl.h"
#include "nthw_fpga_reg_defs_rac.h"
#include "nthw_fpga_reg_defs_rmc.h"
+#include "nthw_fpga_reg_defs_rpf.h"
#include "nthw_fpga_reg_defs_rpl.h"
#include "nthw_fpga_reg_defs_rpp_lr.h"
#include "nthw_fpga_reg_defs_rst9563.h"
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
new file mode 100644
index 0000000000..72f450b85d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RPF_
+#define _NTHW_FPGA_REG_DEFS_RPF_
+
+/* RPF */
+#define RPF_CONTROL (0x7a5bdb50UL)
+#define RPF_CONTROL_KEEP_ALIVE_EN (0x80be3ffcUL)
+#define RPF_CONTROL_PEN (0xb23137b8UL)
+#define RPF_CONTROL_RPP_EN (0xdb51f109UL)
+#define RPF_CONTROL_ST_TGL_EN (0x45a6ecfaUL)
+#define RPF_TS_SORT_PRG (0xff1d137eUL)
+#define RPF_TS_SORT_PRG_MATURING_DELAY (0x2a38e127UL)
+#define RPF_TS_SORT_PRG_TS_AT_EOF (0x9f27d433UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_RPF_ */
--
2.45.0
