From: Oleksandr Kolomeiets <okl-...@napatech.com>
The Key Matcher module checks the values of individual fields of a packet.
It supports both exact match which is implemented with a CAM,
and wildcards which is implemented with a TCAM.
Signed-off-by: Oleksandr Kolomeiets <okl-...@napatech.com>
---
drivers/net/ntnic/include/hw_mod_backend.h | 85 ++++++
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c | 3 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_km.c | 278 ++++++++++++++++++
.../supported/nthw_fpga_9563_055_049_0000.c | 94 +++++-
6 files changed, 461 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_km.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h
b/drivers/net/ntnic/include/hw_mod_backend.h
index 20b10faf5e..f40b33a888 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -32,6 +32,7 @@ void *callocate_mod(struct common_func_s *mod, int sets, ...);
void zero_module_cache(struct common_func_s *mod);
#define ALL_ENTRIES -1000
+#define ALL_BANK_ENTRIES -1001
#define INDEX_TOO_LARGE (NT_LOG(INF, FILTER, "ERROR:%s: Index too large\n",
__func__), -2)
@@ -267,6 +268,89 @@ struct km_func_s {
struct hw_mod_km_v7_s v7;
};
};
+enum hw_km_e {
+ /* functions */
+ HW_KM_RCP_PRESET_ALL = 0,
+ HW_KM_CAM_PRESET_ALL,
+ /* to sync and reset hw with cache - force write all entries in a bank
*/
+ HW_KM_TCAM_BANK_RESET,
+ /* fields */
+ HW_KM_RCP_QW0_DYN = FIELD_START_INDEX,
+ HW_KM_RCP_QW0_OFS,
+ HW_KM_RCP_QW0_SEL_A,
+ HW_KM_RCP_QW0_SEL_B,
+ HW_KM_RCP_QW4_DYN,
+ HW_KM_RCP_QW4_OFS,
+ HW_KM_RCP_QW4_SEL_A,
+ HW_KM_RCP_QW4_SEL_B,
+ HW_KM_RCP_DW8_DYN,
+ HW_KM_RCP_DW8_OFS,
+ HW_KM_RCP_DW8_SEL_A,
+ HW_KM_RCP_DW8_SEL_B,
+ HW_KM_RCP_DW10_DYN,
+ HW_KM_RCP_DW10_OFS,
+ HW_KM_RCP_DW10_SEL_A,
+ HW_KM_RCP_DW10_SEL_B,
+ HW_KM_RCP_SWX_CCH,
+ HW_KM_RCP_SWX_SEL_A,
+ HW_KM_RCP_SWX_SEL_B,
+ HW_KM_RCP_MASK_A,
+ HW_KM_RCP_MASK_B,
+ HW_KM_RCP_DUAL,
+ HW_KM_RCP_PAIRED,
+ HW_KM_RCP_EL_A,
+ HW_KM_RCP_EL_B,
+ HW_KM_RCP_INFO_A,
+ HW_KM_RCP_INFO_B,
+ HW_KM_RCP_FTM_A,
+ HW_KM_RCP_FTM_B,
+ HW_KM_RCP_BANK_A,
+ HW_KM_RCP_BANK_B,
+ HW_KM_RCP_KL_A,
+ HW_KM_RCP_KL_B,
+ HW_KM_RCP_KEYWAY_A,
+ HW_KM_RCP_KEYWAY_B,
+ HW_KM_RCP_SYNERGY_MODE,
+ HW_KM_RCP_DW0_B_DYN,
+ HW_KM_RCP_DW0_B_OFS,
+ HW_KM_RCP_DW2_B_DYN,
+ HW_KM_RCP_DW2_B_OFS,
+ HW_KM_RCP_SW4_B_DYN,
+ HW_KM_RCP_SW4_B_OFS,
+ HW_KM_RCP_SW5_B_DYN,
+ HW_KM_RCP_SW5_B_OFS,
+ HW_KM_CAM_W0,
+ HW_KM_CAM_W1,
+ HW_KM_CAM_W2,
+ HW_KM_CAM_W3,
+ HW_KM_CAM_W4,
+ HW_KM_CAM_W5,
+ HW_KM_CAM_FT0,
+ HW_KM_CAM_FT1,
+ HW_KM_CAM_FT2,
+ HW_KM_CAM_FT3,
+ HW_KM_CAM_FT4,
+ HW_KM_CAM_FT5,
+ HW_KM_TCAM_T,
+ HW_KM_TCI_COLOR,
+ HW_KM_TCI_FT,
+ HW_KM_TCQ_BANK_MASK,
+ HW_KM_TCQ_QUAL
+};
+bool hw_mod_km_present(struct flow_api_backend_s *be);
+int hw_mod_km_alloc(struct flow_api_backend_s *be);
+void hw_mod_km_free(struct flow_api_backend_s *be);
+int hw_mod_km_reset(struct flow_api_backend_s *be);
+int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count);
+int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
+int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int
count);
+int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int
bank, int byte,
+ int byte_val, uint32_t *value_set);
+int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
+int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int
start_record,
+ int count);
struct flm_func_s {
COMMON_FUNC_INFO_S;
@@ -483,6 +567,7 @@ struct flow_api_backend_s {
/* flow filter FPGA modules */
struct cat_func_s cat;
+ struct km_func_s km;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 3d394f9bad..e37bb96331 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -50,6 +50,7 @@ sources = files(
'nthw/flow_api/flow_km.c',
'nthw/flow_api/hw_mod/hw_mod_backend.c',
'nthw/flow_api/hw_mod/hw_mod_cat.c',
+ 'nthw/flow_api/hw_mod/hw_mod_km.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
'nthw/flow_filter/flow_nthw_flm.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c
b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index 3b1d7c5850..c85838519b 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c
@@ -287,6 +287,9 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no,
const struct flow_api_b
if (init_resource_elements(ndev, RES_KM_FLOW_TYPE,
ndev->be.cat.nb_flow_types))
goto err_exit;
+ if (init_resource_elements(ndev, RES_KM_CATEGORY,
ndev->be.km.nb_categories))
+ goto err_exit;
+
if (init_resource_elements(ndev, RES_SLC_LR_RCP,
ndev->be.max_categories))
goto err_exit;
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index 33fb4df126..9d5572f4b2 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -18,6 +18,7 @@ static const struct {
bool (*present)(struct flow_api_backend_s *be);
} module[] = {
{ "CAT", hw_mod_cat_alloc, hw_mod_cat_free, hw_mod_cat_reset,
hw_mod_cat_present },
+ { "KM", hw_mod_km_alloc, hw_mod_km_free, hw_mod_km_reset,
hw_mod_km_present },
};
#define MOD_COUNT (ARRAY_SIZE(module))
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_km.c
b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_km.c
new file mode 100644
index 0000000000..680fcd0af9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_km.c
@@ -0,0 +1,278 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "hw_mod_backend.h"
+
+#define _MOD_ "KM"
+#define _VER_ be->km.ver
+
+#define KM_TCQ_ENTRIES 2048
+#define KM_RCP_MASK_A_SIZE 11
+#define KM_RCP_MASK_D_A_SIZE 12 /* Mask for double size word extractors
for DW8/DW10 */
+#define KM_RCP_MASK_B_SIZE 6
+
+bool hw_mod_km_present(struct flow_api_backend_s *be)
+{
+ return be->iface->get_km_present(be->be_dev);
+}
+
+int hw_mod_km_alloc(struct flow_api_backend_s *be)
+{
+ int nb;
+ _VER_ = be->iface->get_km_version(be->be_dev);
+ NT_LOG(DBG, FILTER, "KM MODULE VERSION %i.%i\n", VER_MAJOR(_VER_),
VER_MINOR(_VER_));
+
+ nb = be->iface->get_nb_km_categories(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(km_categories);
+
+ be->km.nb_categories = (uint32_t)nb;
+
+ nb = be->iface->get_nb_km_cam_banks(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(cam_banks);
+
+ be->km.nb_cam_banks = (uint32_t)nb;
+
+ nb = be->iface->get_nb_km_cam_records(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(cam_records);
+
+ be->km.nb_cam_records = (uint32_t)nb;
+
+ nb = be->iface->get_nb_km_cam_record_words(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(cam_record_words);
+
+ be->km.nb_cam_record_words = (uint32_t)nb;
+
+ nb = be->iface->get_nb_km_tcam_banks(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(tcam_banks);
+
+ be->km.nb_tcam_banks = (uint32_t)nb;
+
+ nb = be->iface->get_nb_km_tcam_bank_width(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(tcam_bank_width);
+
+ be->km.nb_tcam_bank_width = (uint32_t)nb;
+
+ switch (_VER_) {
+ case 7:
+ be->km.nb_km_rcp_mask_a_word_size = 12;
+ be->km.nb_km_rcp_mask_b_word_size = 6;
+
+ if (!callocate_mod((struct common_func_s *)&be->km, 5,
&be->km.v7.rcp,
+ be->km.nb_categories, sizeof(struct
km_v7_rcp_s),
+ &be->km.v7.cam, be->km.nb_cam_banks *
be->km.nb_cam_records,
+ sizeof(struct km_v7_cam_s), &be->km.v7.tcam,
+ be->km.nb_tcam_banks * 4 * 256, sizeof(struct
km_v7_tcam_s),
+ &be->km.v7.tci,
+ be->km.nb_tcam_banks *
be->km.nb_tcam_bank_width,
+ sizeof(struct km_v7_tci_s), &be->km.v7.tcq,
KM_TCQ_ENTRIES,
+ sizeof(struct km_v7_tcq_s)))
+ return -1;
+
+ break;
+
+ /* end case 7 */
+ default:
+ return UNSUP_VER;
+ }
+
+ return 0;
+}
+
+void hw_mod_km_free(struct flow_api_backend_s *be)
+{
+ if (be->km.base) {
+ free(be->km.base);
+ be->km.base = NULL;
+ }
+}
+
+int hw_mod_km_reset(struct flow_api_backend_s *be)
+{
+ uint32_t tcam_v_set[3] = { 0x00000000, 0x00000000, 0x00000000 };
+
+ /* Zero entire cache area */
+ zero_module_cache((struct common_func_s *)(&be->km));
+
+ NT_LOG(DBG, FILTER, "INIT KM RCP\n");
+ hw_mod_km_rcp_flush(be, 0, ALL_ENTRIES);
+
+ /* init CAM - all zero */
+ NT_LOG(DBG, FILTER, "INIT KM CAM\n");
+ hw_mod_km_cam_flush(be, 0, 0, ALL_ENTRIES);
+
+ /* init TCAM - all zero */
+ NT_LOG(DBG, FILTER, "INIT KM TCAM\n");
+
+ for (unsigned int i = 0; i < be->km.nb_tcam_banks; i++) {
+ /* TCAM entries are cache controlled,
+ * thus need to hard reset initially to sync cache with HW
+ */
+ hw_mod_km_tcam_set(be, HW_KM_TCAM_BANK_RESET, i, 0, 0,
tcam_v_set);
+ }
+
+ hw_mod_km_tcam_flush(be, 0, ALL_ENTRIES);
+
+ /* init TCI - all zero */
+ NT_LOG(DBG, FILTER, "INIT KM TCI\n");
+ hw_mod_km_tci_flush(be, 0, 0, ALL_ENTRIES);
+
+ NT_LOG(DBG, FILTER, "INIT KM TCQ\n");
+
+ for (unsigned int i = 0; i < be->km.nb_tcam_bank_width; i++)
+ hw_mod_km_tcq_flush(be, 0, i, be->km.nb_tcam_banks);
+
+ return 0;
+}
+
+int hw_mod_km_rcp_flush(struct flow_api_backend_s *be, int start_idx, int
count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->km.nb_categories;
+
+ if ((unsigned int)(start_idx + count) > be->km.nb_categories)
+ return INDEX_TOO_LARGE;
+
+ return be->iface->km_rcp_flush(be->be_dev, &be->km, start_idx, count);
+}
+
+int hw_mod_km_cam_flush(struct flow_api_backend_s *be, int start_bank, int
start_record, int count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->km.nb_cam_records * be->km.nb_cam_banks;
+
+ unsigned int end = start_bank * be->km.nb_cam_records + start_record +
count;
+
+ if (end > (be->km.nb_cam_banks * be->km.nb_cam_records))
+ return INDEX_TOO_LARGE;
+
+ return be->iface->km_cam_flush(be->be_dev, &be->km, start_bank,
start_record, count);
+}
+
+int hw_mod_km_tcam_flush(struct flow_api_backend_s *be, int start_bank, int
count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->km.nb_tcam_banks * 4 * 256;
+
+ else if (count == ALL_BANK_ENTRIES)
+ count = 4 * 256;
+
+ unsigned int end = start_bank * 4 * 256 + count;
+
+ if (end > (be->km.nb_tcam_banks * 4 * 256))
+ return INDEX_TOO_LARGE;
+
+ return be->iface->km_tcam_flush(be->be_dev, &be->km, start_bank, 0, 0,
count);
+}
+
+static int hw_mod_km_tcam_mod(struct flow_api_backend_s *be, enum hw_km_e
field, int bank,
+ int byte, int byte_val, uint32_t *value_set, int get)
+{
+ unsigned int start_index = bank * 4 * 256 + (int)byte * 256 + byte_val;
+
+ if (start_index >= (be->km.nb_tcam_banks * 4 * 256))
+ return INDEX_TOO_LARGE;
+
+ switch (_VER_) {
+ case 7:
+ switch (field) {
+ case HW_KM_TCAM_BANK_RESET:
+ if (get)
+ return UNSUP_FIELD;
+
+ {
+ int start_idx = bank * 4 * 256;
+
+ for (int i = 0; i < 4 * 256; i++) {
+ be->km.v7.tcam[start_idx + i].t[0] =
value_set[0];
+ be->km.v7.tcam[start_idx + i].t[1] =
value_set[1];
+ be->km.v7.tcam[start_idx + i].t[2] =
value_set[2];
+ be->km.v7.tcam[start_idx + i].dirty = 1;
+ }
+ }
+ break;
+
+ case HW_KM_TCAM_T: {
+ int index = bank * 4 * 256 + byte * 256 + byte_val;
+
+ if (get) {
+ value_set[0] = be->km.v7.tcam[index].t[0];
+ value_set[1] = be->km.v7.tcam[index].t[1];
+ value_set[2] = be->km.v7.tcam[index].t[2];
+
+ } else {
+ /* only change if any bits has to be changed */
+ if (be->km.v7.tcam[index].t[0] != value_set[0]
||
+ be->km.v7.tcam[index].t[1] !=
value_set[1] ||
+ be->km.v7.tcam[index].t[2] !=
value_set[2]) {
+ be->km.v7.tcam[index].t[0] =
value_set[0];
+ be->km.v7.tcam[index].t[1] =
value_set[1];
+ be->km.v7.tcam[index].t[2] =
value_set[2];
+ be->km.v7.tcam[index].dirty = 1;
+ }
+ }
+ }
+ break;
+
+ default:
+ return UNSUP_FIELD;
+ }
+
+ break;
+
+ /* end case 7 */
+ default:
+ return UNSUP_VER;
+ }
+
+ return 0;
+}
+
+int hw_mod_km_tcam_set(struct flow_api_backend_s *be, enum hw_km_e field, int
bank, int byte,
+ int byte_val, uint32_t *value_set)
+{
+ return hw_mod_km_tcam_mod(be, field, bank, byte, byte_val, value_set,
0);
+}
+
+int hw_mod_km_tci_flush(struct flow_api_backend_s *be, int start_bank, int
start_record, int count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->km.nb_tcam_banks * be->km.nb_tcam_bank_width;
+
+ unsigned int end = (int)start_bank * be->km.nb_tcam_bank_width +
start_record + count;
+
+ if (end > (be->km.nb_tcam_banks * be->km.nb_tcam_bank_width))
+ return INDEX_TOO_LARGE;
+
+ return be->iface->km_tci_flush(be->be_dev, &be->km, start_bank,
start_record, count);
+}
+
+int hw_mod_km_tcq_flush(struct flow_api_backend_s *be, int start_bank, int
start_record, int count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->km.nb_tcam_banks * be->km.nb_tcam_bank_width;
+
+ unsigned int end = (int)start_bank * be->km.nb_tcam_bank_width +
start_record + count;
+
+ if (end > (be->km.nb_tcam_banks * be->km.nb_tcam_bank_width))
+ return INDEX_TOO_LARGE;
+
+ return be->iface->km_tcq_flush(be->be_dev, &be->km, start_bank,
start_record, count);
+}
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
index 4efd5aa2f8..a003334a23 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
@@ -667,6 +667,97 @@ static nthw_fpga_register_init_s iic_registers[] = {
{ IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1,
iic_tx_fifo_ocy_fields },
};
+static nthw_fpga_field_init_s km_cam_ctrl_fields[] = {
+ { KM_CAM_CTRL_ADR, 13, 0, 0x0000 },
+ { KM_CAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_cam_data_fields[] = {
+ { KM_CAM_DATA_FT0, 4, 192, 0x0000 }, { KM_CAM_DATA_FT1, 4, 196, 0x0000
},
+ { KM_CAM_DATA_FT2, 4, 200, 0x0000 }, { KM_CAM_DATA_FT3, 4, 204, 0x0000
},
+ { KM_CAM_DATA_FT4, 4, 208, 0x0000 }, { KM_CAM_DATA_FT5, 4, 212, 0x0000
},
+ { KM_CAM_DATA_W0, 32, 0, 0x0000 }, { KM_CAM_DATA_W1, 32, 32, 0x0000 },
+ { KM_CAM_DATA_W2, 32, 64, 0x0000 }, { KM_CAM_DATA_W3, 32, 96, 0x0000 },
+ { KM_CAM_DATA_W4, 32, 128, 0x0000 }, { KM_CAM_DATA_W5, 32, 160, 0x0000
},
+};
+
+static nthw_fpga_field_init_s km_rcp_ctrl_fields[] = {
+ { KM_RCP_CTRL_ADR, 5, 0, 0x0000 },
+ { KM_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_rcp_data_fields[] = {
+ { KM_RCP_DATA_BANK_A, 12, 694, 0x0000 }, { KM_RCP_DATA_BANK_B, 12, 706,
0x0000 },
+ { KM_RCP_DATA_DUAL, 1, 651, 0x0000 }, { KM_RCP_DATA_DW0_B_DYN, 5, 729,
0x0000 },
+ { KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 }, { KM_RCP_DATA_DW10_DYN, 5,
55, 0x0000 },
+ { KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 }, { KM_RCP_DATA_DW10_SEL_A, 2,
68, 0x0000 },
+ { KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 }, { KM_RCP_DATA_DW2_B_DYN, 5,
742, 0x0000 },
+ { KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 }, { KM_RCP_DATA_DW8_DYN, 5,
36, 0x0000 },
+ { KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 }, { KM_RCP_DATA_DW8_SEL_A, 3, 49,
0x0000 },
+ { KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 }, { KM_RCP_DATA_EL_A, 4, 653,
0x0000 },
+ { KM_RCP_DATA_EL_B, 3, 657, 0x0000 }, { KM_RCP_DATA_FTM_A, 16, 662,
0x0000 },
+ { KM_RCP_DATA_FTM_B, 16, 678, 0x0000 }, { KM_RCP_DATA_INFO_A, 1, 660,
0x0000 },
+ { KM_RCP_DATA_INFO_B, 1, 661, 0x0000 }, { KM_RCP_DATA_KEYWAY_A, 1, 725,
0x0000 },
+ { KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 }, { KM_RCP_DATA_KL_A, 4, 718,
0x0000 },
+ { KM_RCP_DATA_KL_B, 3, 722, 0x0000 }, { KM_RCP_DATA_MASK_A, 384, 75,
0x0000 },
+ { KM_RCP_DATA_MASK_B, 192, 459, 0x0000 }, { KM_RCP_DATA_PAIRED, 1, 652,
0x0000 },
+ { KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 }, { KM_RCP_DATA_QW0_OFS, 8, 5,
0x0000 },
+ { KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 }, { KM_RCP_DATA_QW0_SEL_B, 3,
16, 0x0000 },
+ { KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 }, { KM_RCP_DATA_QW4_OFS, 8, 24,
0x0000 },
+ { KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 }, { KM_RCP_DATA_QW4_SEL_B, 2,
34, 0x0000 },
+ { KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 }, { KM_RCP_DATA_SW4_B_OFS, 8,
760, 0x0000 },
+ { KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 }, { KM_RCP_DATA_SW5_B_OFS, 8,
773, 0x0000 },
+ { KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 }, { KM_RCP_DATA_SWX_SEL_A, 1, 73,
0x0000 },
+ { KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 }, { KM_RCP_DATA_SYNERGY_MODE,
2, 727, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_status_fields[] = {
+ { KM_STATUS_TCQ_RDY, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcam_ctrl_fields[] = {
+ { KM_TCAM_CTRL_ADR, 14, 0, 0x0000 },
+ { KM_TCAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcam_data_fields[] = {
+ { KM_TCAM_DATA_T, 72, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tci_ctrl_fields[] = {
+ { KM_TCI_CTRL_ADR, 10, 0, 0x0000 },
+ { KM_TCI_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tci_data_fields[] = {
+ { KM_TCI_DATA_COLOR, 32, 0, 0x0000 },
+ { KM_TCI_DATA_FT, 4, 32, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcq_ctrl_fields[] = {
+ { KM_TCQ_CTRL_ADR, 7, 0, 0x0000 },
+ { KM_TCQ_CTRL_CNT, 5, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcq_data_fields[] = {
+ { KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 },
+ { KM_TCQ_DATA_QUAL, 3, 12, 0x0000 },
+};
+
+static nthw_fpga_register_init_s km_registers[] = {
+ { KM_CAM_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_cam_ctrl_fields },
+ { KM_CAM_DATA, 3, 216, NTHW_FPGA_REG_TYPE_WO, 0, 12, km_cam_data_fields
},
+ { KM_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_rcp_ctrl_fields },
+ { KM_RCP_DATA, 1, 781, NTHW_FPGA_REG_TYPE_WO, 0, 44, km_rcp_data_fields
},
+ { KM_STATUS, 10, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, km_status_fields },
+ { KM_TCAM_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcam_ctrl_fields
},
+ { KM_TCAM_DATA, 5, 72, NTHW_FPGA_REG_TYPE_WO, 0, 1, km_tcam_data_fields
},
+ { KM_TCI_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tci_ctrl_fields },
+ { KM_TCI_DATA, 7, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tci_data_fields },
+ { KM_TCQ_CTRL, 8, 21, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcq_ctrl_fields },
+ { KM_TCQ_DATA, 9, 15, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcq_data_fields },
+};
+
static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] = {
{ MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 },
};
@@ -1311,6 +1402,7 @@ static nthw_fpga_module_init_s fpga_modules[] = {
{ MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22,
iic_registers },
{ MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, 22,
iic_registers },
{ MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24960, 22,
iic_registers },
+ { MOD_KM, 0, MOD_KM, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1024, 11,
km_registers },
{
MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2,
10240, 44,
mac_pcs_registers
@@ -1488,5 +1580,5 @@ static nthw_fpga_prod_param_s product_parameters[] = {
};
nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = {
- 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 16,
fpga_modules,
+ 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 17,
fpga_modules,
};
--
2.45.0
