[PATCH v1 21/30] net/i40e/base: make register dump read-only

[Anatoly Burakov]

From: Radoslaw Tyl <radoslawx....@intel.com>

Currently, when registers are dumped, the data inside them is changed, so
repeated dumps lead to unexpected results. Fix this by making register list
read-only.

Signed-off-by: Radoslaw Tyl <radoslawx....@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com>
---
 drivers/net/i40e/base/i40e_diag.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/i40e/base/i40e_diag.c 
b/drivers/net/i40e/base/i40e_diag.c
index b3c4cfd3aa..4ca102cdd5 100644
--- a/drivers/net/i40e/base/i40e_diag.c
+++ b/drivers/net/i40e/base/i40e_diag.c
@@ -55,7 +55,7 @@ static enum i40e_status_code 
i40e_diag_reg_pattern_test(struct i40e_hw *hw,
        return I40E_SUCCESS;
 }
 
-static struct i40e_diag_reg_test_info i40e_reg_list[] = {
+static const struct i40e_diag_reg_test_info i40e_reg_list[] = {
        /* offset               mask         elements   stride */
        {I40E_QTX_CTL(0),       0x0000FFBF, 1, I40E_QTX_CTL(1) - 
I40E_QTX_CTL(0)},
        {I40E_PFINT_ITR0(0),    0x00000FFF, 3, I40E_PFINT_ITR0(1) - 
I40E_PFINT_ITR0(0)},
@@ -81,28 +81,28 @@ enum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw)
 {
        enum i40e_status_code ret_code = I40E_SUCCESS;
        u32 reg, mask;
+       u32 elements;
        u32 i, j;
 
        for (i = 0; i40e_reg_list[i].offset != 0 &&
                                             ret_code == I40E_SUCCESS; i++) {
 
+               elements = i40e_reg_list[i].elements;
                /* set actual reg range for dynamically allocated resources */
                if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
                    hw->func_caps.num_tx_qp != 0)
-                       i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
+                       elements = hw->func_caps.num_tx_qp;
                if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
                     i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
                     i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
                     i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
                     i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
                    hw->func_caps.num_msix_vectors != 0)
-                       i40e_reg_list[i].elements =
-                               hw->func_caps.num_msix_vectors - 1;
+                       elements = hw->func_caps.num_msix_vectors - 1;
 
                /* test register access */
                mask = i40e_reg_list[i].mask;
-               for (j = 0; j < i40e_reg_list[i].elements &&
-                           ret_code == I40E_SUCCESS; j++) {
+               for (j = 0; j < elements && ret_code == I40E_SUCCESS; j++) {
                        reg = i40e_reg_list[i].offset
                                + (j * i40e_reg_list[i].stride);
                        ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
-- 
2.43.5