Hi Gagan,
I think this patch shall come before the 4th patch: [v1 4/7] crypto/dpaa2_sec: enhance pdcp FLC handling
- Hemant On 06-08-2024 14:11, Gagandeep Singh wrote:
From: Jun Yang <jun.y...@nxp.com> Configure flow steering action with FLC enabled to align stashing setting with RSS configuration. Signed-off-by: Jun Yang <jun.y...@nxp.com> Acked-by: Hemant Agrawal <hemant.agra...@nxp.com> --- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 44 +++++++++++++++++++++++++ drivers/net/dpaa2/dpaa2_ethdev.c | 25 +++++++------- 2 files changed, 58 insertions(+), 11 deletions(-) diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index 169c7917ea..4c30e6db18 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -179,6 +179,7 @@ struct __rte_cache_aligned dpaa2_queue { uint16_t resv; uint64_t offloads; uint64_t lpbk_cntx; + uint8_t data_stashing_off; };struct swp_active_dqs {@@ -463,6 +464,49 @@ struct qbman_result *get_swp_active_dqs(uint16_t dpio_index) return rte_global_active_dqs_list[dpio_index].global_active_dqs; }+/* 00 00 00 - last 6 bit represent data, annotation,+ * context stashing setting 01 01 00 (0x14) + * (in following order ->DS AS CS) + * to enable 1 line data, 1 line annotation. + * For LX2, this setting should be 01 00 00 (0x10) + */ +#define DPAA2_FLC_STASHING_MAX_BIT_SIZE 2 +#define DPAA2_FLC_STASHING_MAX_CACHE_LINE \ + ((1ULL << DPAA2_FLC_STASHING_MAX_BIT_SIZE) - 1) + +enum dpaa2_flc_stashing_type { + DPAA2_FLC_CNTX_STASHING = 0, + DPAA2_FLC_ANNO_STASHING = + DPAA2_FLC_CNTX_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE, + DPAA2_FLC_DATA_STASHING = + DPAA2_FLC_ANNO_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE, + DPAA2_FLC_END_STASHING = + DPAA2_FLC_DATA_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE +}; + +#define DPAA2_STASHING_ALIGN_SIZE (1 << DPAA2_FLC_END_STASHING) + +static inline void +dpaa2_flc_stashing_set(enum dpaa2_flc_stashing_type type, + uint8_t cache_line, uint64_t *flc) +{ + RTE_ASSERT(cache_line <= DPAA2_FLC_STASHING_MAX_CACHE_LINE); + RTE_ASSERT(type == DPAA2_FLC_CNTX_STASHING || + type == DPAA2_FLC_ANNO_STASHING || + type == DPAA2_FLC_DATA_STASHING); + + (*flc) &= ~(DPAA2_FLC_STASHING_MAX_CACHE_LINE << type); + (*flc) |= (cache_line << type); +} + +static inline void +dpaa2_flc_stashing_clear_all(uint64_t *flc) +{ + dpaa2_flc_stashing_set(DPAA2_FLC_CNTX_STASHING, 0, flc); + dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 0, flc); + dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, flc); +} + static inline void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs) { diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 449bbda7ca..726bc0cf3e 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -786,17 +786,20 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { options |= DPNI_QUEUE_OPT_FLC; cfg.flc.stash_control = true; - cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; - /* 00 00 00 - last 6 bit represent annotation, context stashing, - * data stashing setting 01 01 00 (0x14) - * (in following order ->DS AS CS) - * to enable 1 line data, 1 line annotation. - * For LX2, this setting should be 01 00 00 (0x10) - */ - if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) - cfg.flc.value |= 0x10; - else - cfg.flc.value |= 0x14; + dpaa2_flc_stashing_clear_all(&cfg.flc.value); + if (getenv("DPAA2_DATA_STASHING_OFF")) { + dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, + &cfg.flc.value); + dpaa2_q->data_stashing_off = 1; + } else { + dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1, + &cfg.flc.value); + dpaa2_q->data_stashing_off = 0; + } + if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) { + dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1, + &cfg.flc.value); + } } ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, dpaa2_q->tc_index, flow_id, options, &cfg);
