From: Karol Kolacinski <karol.kolacin...@intel.com>
Add an interface to clear the timestamp memory block for E822 and ETH56G
based devices.
Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com>
Signed-off-by: Ian Stokes <ian.sto...@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 65 +++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_ptp_hw.h | 2 +
2 files changed, 67 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index df3e3e77bd..ac01de3e37 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1481,6 +1481,25 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port,
u8 idx)
return 0;
}
+/**
+ * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
+ * @hw: pointer to the HW struct
+ */
+static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
+{
+ unsigned int port;
+
+ for (port = 0; port < hw->max_phy_port; port++) {
+ if (!(hw->ena_lports & BIT(port)))
+ continue;
+
+ ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
+ 0);
+ ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
+ 0);
+ }
+}
+
/**
* ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time
* @hw: pointer to the HW struct
@@ -2911,6 +2930,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8
idx)
return 0;
}
+/**
+ * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block
+ * @hw: pointer to the HW struct
+ * @quad: the quad to read from
+ *
+ * Clear all timestamps from the PHY quad block that is shared between the
+ * internal PHYs on the E822 devices.
+ */
+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad)
+{
+ ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
+ ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
+}
+
+/**
+ * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks
+ * @hw: pointer to the HW struct
+ */
+static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)
+{
+ u8 quad;
+
+ for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
+ ice_ptp_reset_ts_memory_quad_e822(hw, quad);
+ }
+}
+
/**
* ice_ptp_set_vernier_wl - Set the window length for vernier calibration
* @hw: pointer to the HW struct
@@ -5969,6 +6015,25 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
return err;
}
+/**
+ * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
+ * @hw: pointer to the HW struct
+ */
+void ice_ptp_reset_ts_memory(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_ETH56G:
+ ice_ptp_reset_ts_memory_eth56g(hw);
+ break;
+ case ICE_PHY_E822:
+ ice_ptp_reset_ts_memory_e822(hw);
+ break;
+ case ICE_PHY_E810:
+ default:
+ return;
+ }
+}
+
/**
* ice_ptp_init_phc - Initialize PTP hardware clock
* @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index f3c0846255..3bd4e27811 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -142,6 +142,7 @@ int
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
int
ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
+void ice_ptp_reset_ts_memory(struct ice_hw *hw);
int ice_ptp_init_phc(struct ice_hw *hw);
bool refsync_pin_id_valid(struct ice_hw *hw, u8 id);
int
@@ -165,6 +166,7 @@ ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port,
u64 *incval);
int
ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,
u64 *tx_ts, u64 *rx_ts);
+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);
int
ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
enum ice_clk_src *clk_src);
--
2.43.0
