[PATCH] net/mlx5: fix HWS GRE OPTION item validation

[Gregory Etelson]

1. GRE_OPTION flow item validation required both item spec and mask.

HWS pattern template provides item mask only.

The patch removes spec requirement in HWS GRE_OPTION item validation.

2. In non-HWS setup, GRE_OPTION flow item validation for the checksum and
sequence item parameters require group value.
HWS pattern template does not have a group.

The patch removes group validations for GRE_OPTION item.

Fixes: 113feae56db6 ("net/mlx5: validate HWS template items")
Signed-off-by: Gregory Etelson <getel...@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 7bcbbc74b5..5e4e45eb3e 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -3388,7 +3388,7 @@ mlx5_flow_validate_item_gre_option(struct rte_eth_dev 
*dev,
                return rte_flow_error_set(error, ENOTSUP,
                                          RTE_FLOW_ERROR_TYPE_ITEM, item,
                                          "GRE option following a wrong item");
-       if (!spec || !mask)
+       if ((!spec && !mlx5_hws_active(dev)) || !mask)
                return rte_flow_error_set(error, EINVAL,
                                          RTE_FLOW_ERROR_TYPE_ITEM, item,
                                          "At least one field 
gre_option(checksum/key/sequence) must be specified");
@@ -3414,18 +3414,21 @@ mlx5_flow_validate_item_gre_option(struct rte_eth_dev 
*dev,
                                                  RTE_FLOW_ERROR_TYPE_ITEM,
                                                  item,
                                                  "Sequence bit must be on");
-       if (mask->checksum_rsvd.checksum || mask->sequence.sequence) {
-               if (priv->sh->steering_format_version ==
-                   MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
-                   ((attr->group || (attr->transfer && priv->fdb_def_rule)) &&
-                    !priv->sh->misc5_cap) ||
-                   (!(priv->sh->tunnel_header_0_1 &&
-                      priv->sh->tunnel_header_2_3) &&
-                   !attr->group && (!attr->transfer || !priv->fdb_def_rule)))
-                       return rte_flow_error_set(error, EINVAL,
-                                                 RTE_FLOW_ERROR_TYPE_ITEM,
-                                                 item,
-                                                 "Checksum/Sequence not 
supported");
+       if (!mlx5_hws_active(dev)) {
+               if (mask->checksum_rsvd.checksum || mask->sequence.sequence) {
+                       if (priv->sh->steering_format_version ==
+                           MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 ||
+                           ((attr->group ||
+                             (attr->transfer && priv->fdb_def_rule)) &&
+                            !priv->sh->misc5_cap) ||
+                           (!(priv->sh->tunnel_header_0_1 &&
+                              priv->sh->tunnel_header_2_3) &&
+                            !attr->group &&
+                            (!attr->transfer || !priv->fdb_def_rule)))
+                               return rte_flow_error_set
+                                       (error, EINVAL, 
RTE_FLOW_ERROR_TYPE_ITEM,
+                                        item, "Checksum/Sequence not 
supported");
+               }
        }
        ret = mlx5_flow_item_acceptable
                (dev, item, (const uint8_t *)mask,
-- 
2.43.0