Implementing the VxLAN last reserved byte modification.
Following the RFC, the field is only 1 byte and needs to
use the field_length as 8 instead of the real dst_field->size.
Signed-off-by: Rongwei Liu <rongw...@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
doc/guides/nics/mlx5.rst | 5 +++++
drivers/net/mlx5/mlx5_flow_dv.c | 12 ++++++++++++
drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
3 files changed, 22 insertions(+)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index b5928d40b2..8b3aaf5aac 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -637,6 +637,11 @@ Limitations
- Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
- Modification of the 802.1Q tag is not supported.
- Modification of VXLAN network or GENEVE network ID is supported only for
HW steering.
+ - Modification of the VXLAN header is supported with below limitations:
+
+ - Only for HW steering (``dv_flow_en=2``).
+ - Support VNI and the last reserved byte modifications for traffic with
default
+ UDP destination port. 4789 for VXLAN and VXLAN-GBP, 4790 for VXLAN-GPE.
- Modification of GENEVE network ID is not supported when configured
``FLEX_PARSER_PROFILE_ENABLE`` supports Geneve TLV options.
See :ref:`mlx5_firmware_config` for more flex parser information.
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 06f5427abf..99abb2f2fb 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1439,6 +1439,8 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,
case RTE_FLOW_FIELD_VXLAN_VNI:
case RTE_FLOW_FIELD_GENEVE_VNI:
return 24;
+ case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
+ return 8;
case RTE_FLOW_FIELD_GTP_TEID:
case RTE_FLOW_FIELD_MPLS:
case RTE_FLOW_FIELD_TAG:
@@ -2038,6 +2040,16 @@ mlx5_flow_field_id_to_modify_info
else
info[idx].offset = off_be;
break;
+ case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
+ MLX5_ASSERT(data->offset + width <= 8);
+ /* Last_rsvd is on bits 7-0 of TUNNEL_HDR_DW_1. */
+ off_be = 8 - (data->offset + width);
+ info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_TUNNEL_HDR_DW_1};
+ if (mask)
+ mask[idx] = flow_modify_info_mask_8(width, off_be);
+ else
+ info[idx].offset = off_be;
+ break;
case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
MLX5_ASSERT(data->offset + width <= 8);
modi_id = flow_geneve_opt_modi_field_get(priv, data);
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 63194935a3..01362ae121 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -1385,6 +1385,10 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,
value = *(const uint8_t *)item.spec;
value = rte_cpu_to_be_32(value << 8);
item.spec = &value;
+ } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) {
+ value = *(const uint8_t *)item.spec << 24;
+ value = rte_cpu_to_be_32(value);
+ item.spec = &value;
}
} else {
type = conf->operation == RTE_FLOW_MODIFY_SET ?
@@ -5580,6 +5584,7 @@ flow_hw_validate_modify_field_level(const struct
rte_flow_field_data *data,
case RTE_FLOW_FIELD_ESP_SPI:
case RTE_FLOW_FIELD_ESP_SEQ_NUM:
case RTE_FLOW_FIELD_VXLAN_VNI:
+ case RTE_FLOW_FIELD_VXLAN_LAST_RSVD:
case RTE_FLOW_FIELD_GENEVE_VNI:
case RTE_FLOW_FIELD_GENEVE_OPT_TYPE:
case RTE_FLOW_FIELD_GENEVE_OPT_CLASS:
--
2.27.0
