Add ntnic base interfaces for: link, NIM, sensors, statistics.
Signed-off-by: Serhii Iliushyk <sil-...@napatech.com>
---
drivers/net/ntnic/include/nt4ga_link.h | 132 +++++
drivers/net/ntnic/include/ntnic_dbs.h | 356 ++++++++++++
drivers/net/ntnic/include/ntnic_nim.h | 160 ++++++
.../include/ntnic_nthw_fpga_rst_nt200a0x.h | 82 +++
drivers/net/ntnic/include/ntnic_sensor.h | 515 ++++++++++++++++++
drivers/net/ntnic/include/ntnic_stat.h | 291 ++++++++++
6 files changed, 1536 insertions(+)
create mode 100644 drivers/net/ntnic/include/nt4ga_link.h
create mode 100644 drivers/net/ntnic/include/ntnic_dbs.h
create mode 100644 drivers/net/ntnic/include/ntnic_nim.h
create mode 100644 drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
create mode 100644 drivers/net/ntnic/include/ntnic_sensor.h
create mode 100644 drivers/net/ntnic/include/ntnic_stat.h
diff --git a/drivers/net/ntnic/include/nt4ga_link.h
b/drivers/net/ntnic/include/nt4ga_link.h
new file mode 100644
index 0000000000..49e1c5d672
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_link.h
@@ -0,0 +1,132 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NT4GA_LINK_H_
+#define NT4GA_LINK_H_
+
+#include "common_adapter_defs.h"
+#include "nthw_drv.h"
+#include "ntnic_nim.h"
+#include "ntnic_nthw_fpga_rst_nt200a0x.h"
+
+/*
+ * Link state.\n
+ * Just after start of ntservice the link state might be unknown since the
+ * monitoring routine is busy reading NIM state and NIM data. This might also
+ * be the case after a NIM is plugged into an interface.
+ * The error state indicates a HW reading error.
+ */
+enum nt_link_state_e {
+ NT_LINK_STATE_UNKNOWN = 0, /* The link state has not been read yet
*/
+ NT_LINK_STATE_DOWN = 1, /* The link state is DOWN */
+ NT_LINK_STATE_UP = 2, /* The link state is UP */
+ NT_LINK_STATE_ERROR = 3 /* The link state could not be read */
+};
+
+typedef enum nt_link_state_e nt_link_state_t, *nt_link_state_p;
+
+/*
+ * Link duplex mode
+ */
+enum nt_link_duplex_e {
+ NT_LINK_DUPLEX_UNKNOWN = 0,
+ NT_LINK_DUPLEX_HALF = 0x01, /* Half duplex */
+ NT_LINK_DUPLEX_FULL = 0x02, /* Full duplex */
+};
+
+typedef enum nt_link_duplex_e nt_link_duplex_t;
+
+/*
+ * Link loopback mode
+ */
+enum nt_link_loopback_e {
+ NT_LINK_LOOPBACK_OFF = 0,
+ NT_LINK_LOOPBACK_HOST = 0x01, /* Host loopback mode */
+ NT_LINK_LOOPBACK_LINE = 0x02, /* Line loopback mode */
+};
+
+/*
+ * Link MDI mode
+ */
+enum nt_link_mdi_e {
+ NT_LINK_MDI_NA = 0,
+ NT_LINK_MDI_AUTO = 0x01,/* MDI auto */
+ NT_LINK_MDI_MDI = 0x02, /* MDI mode */
+ NT_LINK_MDI_MDIX = 0x04,/* MDIX mode */
+};
+
+typedef enum nt_link_mdi_e nt_link_mdi_t;
+
+/*
+ * Link Auto/Manual mode
+ */
+enum nt_link_auto_neg_e {
+ NT_LINK_AUTONEG_NA = 0,
+ NT_LINK_AUTONEG_MANUAL = 0x01,
+ NT_LINK_AUTONEG_OFF = NT_LINK_AUTONEG_MANUAL, /* Auto negotiation OFF
*/
+ NT_LINK_AUTONEG_AUTO = 0x02,
+ NT_LINK_AUTONEG_ON = NT_LINK_AUTONEG_AUTO, /* Auto negotiation ON
*/
+};
+
+typedef enum nt_link_auto_neg_e nt_link_auto_neg_t;
+
+/*
+ * Callback functions to setup mac, pcs and phy
+ */
+typedef struct link_state_s {
+ bool link_disabled;
+ bool nim_present;
+ bool lh_nim_absent;
+ bool link_up;
+ enum nt_link_state_e link_state;
+ enum nt_link_state_e link_state_latched;
+} link_state_t;
+
+/*
+ * Link speed.
+ * Note this is a bitmask.
+ */
+enum nt_link_speed_e {
+ NT_LINK_SPEED_UNKNOWN = 0,
+ NT_LINK_SPEED_10M = 0x01, /* 10 Mbps */
+ NT_LINK_SPEED_100M = 0x02, /* 100 Mbps */
+ NT_LINK_SPEED_1G = 0x04,/* 1 Gbps (Autoneg only) */
+ NT_LINK_SPEED_10G = 0x08, /* 10 Gbps (Autoneg only) */
+ NT_LINK_SPEED_40G = 0x10, /* 40 Gbps (Autoneg only) */
+ NT_LINK_SPEED_100G = 0x20, /* 100 Gbps (Autoneg only) */
+ NT_LINK_SPEED_50G = 0x40, /* 50 Gbps (Autoneg only) */
+ NT_LINK_SPEED_25G = 0x80, /* 25 Gbps (Autoneg only) */
+ NT_LINK_SPEED_END /* always keep this entry as the last in enum */
+};
+typedef enum nt_link_speed_e nt_link_speed_t;
+
+typedef struct link_info_s {
+ enum nt_link_speed_e link_speed;
+ enum nt_link_duplex_e link_duplex;
+ enum nt_link_auto_neg_e link_auto_neg;
+} link_info_t;
+
+typedef struct port_action_s {
+ bool port_disable;
+ enum nt_link_speed_e port_speed;
+ enum nt_link_duplex_e port_duplex;
+ uint32_t port_lpbk_mode;
+} port_action_t;
+
+typedef union adapter_var_s {
+ nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* First field in all
the adaptors type */
+} adapter_var_u;
+
+typedef struct nt4ga_link_s {
+ link_state_t link_state[NUM_ADAPTER_PORTS_MAX];
+ link_info_t link_info[NUM_ADAPTER_PORTS_MAX];
+ port_action_t port_action[NUM_ADAPTER_PORTS_MAX];
+ uint32_t speed_capa;
+ /* */
+ bool variables_initialized;
+ adapter_var_u u;
+} nt4ga_link_t;
+
+#endif /* NT4GA_LINK_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_dbs.h
b/drivers/net/ntnic/include/ntnic_dbs.h
new file mode 100644
index 0000000000..cf3cc46024
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_dbs.h
@@ -0,0 +1,356 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_DBS_H_
+#define _NTNIC_DBS_H_
+
+#include "nthw_fpga_model.h"
+
+#define NT_DBS_RX_QUEUES_MAX (128)
+#define NT_DBS_TX_QUEUES_MAX (128)
+
+/*
+ * Struct for implementation of memory bank shadows
+ */
+
+/* DBS_RX_AM_DATA */
+struct nthw_dbs_rx_am_data_s {
+ uint64_t guest_physical_address;
+ uint32_t enable;
+ uint32_t host_id;
+ uint32_t packed;
+ uint32_t int_enable;
+};
+
+/* DBS_TX_AM_DATA */
+struct nthw_dbs_tx_am_data_s {
+ uint64_t guest_physical_address;
+ uint32_t enable;
+ uint32_t host_id;
+ uint32_t packed;
+ uint32_t int_enable;
+};
+
+/* DBS_RX_UW_DATA */
+struct nthw_dbs_rx_uw_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t packed;
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+};
+
+/* DBS_TX_UW_DATA */
+struct nthw_dbs_tx_uw_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t packed;
+ uint32_t int_enable;
+ uint32_t vec;
+ uint32_t istk;
+ uint32_t in_order;
+};
+
+/* DBS_RX_DR_DATA */
+struct nthw_dbs_rx_dr_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t header;
+ uint32_t packed;
+};
+
+/* DBS_TX_DR_DATA */
+struct nthw_dbs_tx_dr_data_s {
+ uint64_t guest_physical_address;
+ uint32_t host_id;
+ uint32_t queue_size;
+ uint32_t header;
+ uint32_t port;
+ uint32_t packed;
+};
+
+/* DBS_TX_QP_DATA */
+struct nthw_dbs_tx_qp_data_s {
+ uint32_t virtual_port;
+};
+
+struct nthw_dbs_tx_qos_data_s {
+ uint32_t enable;
+ uint32_t ir;
+ uint32_t bs;
+};
+
+struct nthw_dbs_s {
+ nthw_fpga_t *mp_fpga;
+ nthw_module_t *mp_mod_dbs;
+ int mn_instance;
+
+ int mn_param_dbs_present;
+
+ nthw_register_t *mp_reg_rx_control;
+ nthw_field_t *mp_fld_rx_control_last_queue;
+ nthw_field_t *mp_fld_rx_control_avail_monitor_enable;
+ nthw_field_t *mp_fld_rx_control_avail_monitor_scan_speed;
+ nthw_field_t *mp_fld_rx_control_used_write_enable;
+ nthw_field_t *mp_fld_rx_control_used_writer_update_speed;
+ nthw_field_t *mp_fld_rx_control_rx_queues_enable;
+
+ nthw_register_t *mp_reg_tx_control;
+ nthw_field_t *mp_fld_tx_control_last_queue;
+ nthw_field_t *mp_fld_tx_control_avail_monitor_enable;
+ nthw_field_t *mp_fld_tx_control_avail_monitor_scan_speed;
+ nthw_field_t *mp_fld_tx_control_used_write_enable;
+ nthw_field_t *mp_fld_tx_control_used_writer_update_speed;
+ nthw_field_t *mp_fld_tx_control_tx_queues_enable;
+
+ nthw_register_t *mp_reg_rx_init;
+ nthw_field_t *mp_fld_rx_init_init;
+ nthw_field_t *mp_fld_rx_init_queue;
+ nthw_field_t *mp_fld_rx_init_busy;
+
+ nthw_register_t *mp_reg_rx_init_val;
+ nthw_field_t *mp_fld_rx_init_val_idx;
+ nthw_field_t *mp_fld_rx_init_val_ptr;
+
+ nthw_register_t *mp_reg_rx_ptr;
+ nthw_field_t *mp_fld_rx_ptr_ptr;
+ nthw_field_t *mp_fld_rx_ptr_queue;
+ nthw_field_t *mp_fld_rx_ptr_valid;
+
+ nthw_register_t *mp_reg_tx_init;
+ nthw_field_t *mp_fld_tx_init_init;
+ nthw_field_t *mp_fld_tx_init_queue;
+ nthw_field_t *mp_fld_tx_init_busy;
+
+ nthw_register_t *mp_reg_tx_init_val;
+ nthw_field_t *mp_fld_tx_init_val_idx;
+ nthw_field_t *mp_fld_tx_init_val_ptr;
+
+ nthw_register_t *mp_reg_tx_ptr;
+ nthw_field_t *mp_fld_tx_ptr_ptr;
+ nthw_field_t *mp_fld_tx_ptr_queue;
+ nthw_field_t *mp_fld_tx_ptr_valid;
+
+ nthw_register_t *mp_reg_rx_idle;
+ nthw_field_t *mp_fld_rx_idle_idle;
+ nthw_field_t *mp_fld_rx_idle_queue;
+ nthw_field_t *mp_fld_rx_idle_busy;
+
+ nthw_register_t *mp_reg_tx_idle;
+ nthw_field_t *mp_fld_tx_idle_idle;
+ nthw_field_t *mp_fld_tx_idle_queue;
+ nthw_field_t *mp_fld_tx_idle_busy;
+
+ nthw_register_t *mp_reg_rx_avail_monitor_control;
+ nthw_field_t *mp_fld_rx_avail_monitor_control_adr;
+ nthw_field_t *mp_fld_rx_avail_monitor_control_cnt;
+
+ nthw_register_t *mp_reg_rx_avail_monitor_data;
+ nthw_field_t *mp_fld_rx_avail_monitor_data_guest_physical_address;
+ nthw_field_t *mp_fld_rx_avail_monitor_data_enable;
+ nthw_field_t *mp_fld_rx_avail_monitor_data_host_id;
+ nthw_field_t *mp_fld_rx_avail_monitor_data_packed;
+ nthw_field_t *mp_fld_rx_avail_monitor_data_int;
+
+ nthw_register_t *mp_reg_tx_avail_monitor_control;
+ nthw_field_t *mp_fld_tx_avail_monitor_control_adr;
+ nthw_field_t *mp_fld_tx_avail_monitor_control_cnt;
+
+ nthw_register_t *mp_reg_tx_avail_monitor_data;
+ nthw_field_t *mp_fld_tx_avail_monitor_data_guest_physical_address;
+ nthw_field_t *mp_fld_tx_avail_monitor_data_enable;
+ nthw_field_t *mp_fld_tx_avail_monitor_data_host_id;
+ nthw_field_t *mp_fld_tx_avail_monitor_data_packed;
+ nthw_field_t *mp_fld_tx_avail_monitor_data_int;
+
+ nthw_register_t *mp_reg_rx_used_writer_control;
+ nthw_field_t *mp_fld_rx_used_writer_control_adr;
+ nthw_field_t *mp_fld_rx_used_writer_control_cnt;
+
+ nthw_register_t *mp_reg_rx_used_writer_data;
+ nthw_field_t *mp_fld_rx_used_writer_data_guest_physical_address;
+ nthw_field_t *mp_fld_rx_used_writer_data_host_id;
+ nthw_field_t *mp_fld_rx_used_writer_data_queue_size;
+ nthw_field_t *mp_fld_rx_used_writer_data_packed;
+ nthw_field_t *mp_fld_rx_used_writer_data_int;
+ nthw_field_t *mp_fld_rx_used_writer_data_vec;
+ nthw_field_t *mp_fld_rx_used_writer_data_istk;
+
+ nthw_register_t *mp_reg_tx_used_writer_control;
+ nthw_field_t *mp_fld_tx_used_writer_control_adr;
+ nthw_field_t *mp_fld_tx_used_writer_control_cnt;
+
+ nthw_register_t *mp_reg_tx_used_writer_data;
+ nthw_field_t *mp_fld_tx_used_writer_data_guest_physical_address;
+ nthw_field_t *mp_fld_tx_used_writer_data_host_id;
+ nthw_field_t *mp_fld_tx_used_writer_data_queue_size;
+ nthw_field_t *mp_fld_tx_used_writer_data_packed;
+ nthw_field_t *mp_fld_tx_used_writer_data_int;
+ nthw_field_t *mp_fld_tx_used_writer_data_vec;
+ nthw_field_t *mp_fld_tx_used_writer_data_istk;
+ nthw_field_t *mp_fld_tx_used_writer_data_in_order;
+
+ nthw_register_t *mp_reg_rx_descriptor_reader_control;
+ nthw_field_t *mp_fld_rx_descriptor_reader_control_adr;
+ nthw_field_t *mp_fld_rx_descriptor_reader_control_cnt;
+
+ nthw_register_t *mp_reg_rx_descriptor_reader_data;
+ nthw_field_t *mp_fld_rx_descriptor_reader_data_guest_physical_address;
+ nthw_field_t *mp_fld_rx_descriptor_reader_data_host_id;
+ nthw_field_t *mp_fld_rx_descriptor_reader_data_queue_size;
+ nthw_field_t *mp_fld_rx_descriptor_reader_data_header;
+ nthw_field_t *mp_fld_rx_descriptor_reader_data_packed;
+
+ nthw_register_t *mp_reg_tx_descriptor_reader_control;
+ nthw_field_t *mp_fld_tx_descriptor_reader_control_adr;
+ nthw_field_t *mp_fld_tx_descriptor_reader_control_cnt;
+
+ nthw_register_t *mp_reg_tx_descriptor_reader_data;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_guest_physical_address;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_host_id;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_queue_size;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_port;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_header;
+ nthw_field_t *mp_fld_tx_descriptor_reader_data_packed;
+
+ nthw_register_t *mp_reg_tx_queue_property_control;
+ nthw_field_t *mp_fld_tx_queue_property_control_adr;
+ nthw_field_t *mp_fld_tx_queue_property_control_cnt;
+
+ nthw_register_t *mp_reg_tx_queue_property_data;
+ nthw_field_t *mp_fld_tx_queue_property_data_v_port;
+
+ nthw_register_t *mp_reg_tx_queue_qos_control;
+ nthw_field_t *mp_reg_tx_queue_qos_control_adr;
+ nthw_field_t *mp_reg_tx_queue_qos_control_cnt;
+
+ nthw_register_t *mp_reg_tx_queue_qos_data;
+ nthw_field_t *mp_reg_tx_queue_qos_data_en;
+ nthw_field_t *mp_reg_tx_queue_qos_data_ir;
+ nthw_field_t *mp_reg_tx_queue_qos_data_bs;
+
+ nthw_register_t *mp_reg_tx_queue_qos_rate;
+ nthw_field_t *mp_reg_tx_queue_qos_rate_mul;
+ nthw_field_t *mp_reg_tx_queue_qos_rate_div;
+
+ struct nthw_dbs_rx_am_data_s m_rx_am_shadow[NT_DBS_RX_QUEUES_MAX];
+ struct nthw_dbs_rx_uw_data_s m_rx_uw_shadow[NT_DBS_RX_QUEUES_MAX];
+ struct nthw_dbs_rx_dr_data_s m_rx_dr_shadow[NT_DBS_RX_QUEUES_MAX];
+
+ struct nthw_dbs_tx_am_data_s m_tx_am_shadow[NT_DBS_TX_QUEUES_MAX];
+ struct nthw_dbs_tx_uw_data_s m_tx_uw_shadow[NT_DBS_TX_QUEUES_MAX];
+ struct nthw_dbs_tx_dr_data_s m_tx_dr_shadow[NT_DBS_TX_QUEUES_MAX];
+ struct nthw_dbs_tx_qp_data_s m_tx_qp_shadow[NT_DBS_TX_QUEUES_MAX];
+ struct nthw_dbs_tx_qos_data_s m_tx_qos_shadow[NT_DBS_TX_QUEUES_MAX];
+};
+
+typedef struct nthw_dbs_s nthw_dbs_t;
+
+nthw_dbs_t *nthw_dbs_new(void);
+void nthw_dbs_delete(nthw_dbs_t *p);
+int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void dbs_reset(nthw_dbs_t *p);
+
+int dbs_reset_rx_control(nthw_dbs_t *p);
+int dbs_reset_tx_control(nthw_dbs_t *p);
+int set_rx_control(nthw_dbs_t *p,
+ uint32_t last_queue,
+ uint32_t avail_monitor_enable,
+ uint32_t avail_monitor_speed,
+ uint32_t used_write_enable,
+ uint32_t used_write_speed,
+ uint32_t rx_queue_enable);
+int nthw_dbs_get_rx_control(nthw_dbs_t *p,
+ uint32_t *last_queue,
+ uint32_t *avail_monitor_enable,
+ uint32_t *avail_monitor_speed,
+ uint32_t *used_write_enable,
+ uint32_t *used_write_speed,
+ uint32_t *rx_queue_enable);
+int set_tx_control(nthw_dbs_t *p,
+ uint32_t last_queue,
+ uint32_t avail_monitor_enable,
+ uint32_t avail_monitor_speed,
+ uint32_t used_write_enable,
+ uint32_t used_write_speed,
+ uint32_t tx_queue_enable);
+int nthw_dbs_get_tx_control(nthw_dbs_t *p,
+ uint32_t *last_queue,
+ uint32_t *avail_monitor_enable,
+ uint32_t *avail_monitor_speed,
+ uint32_t *used_write_enable,
+ uint32_t *used_write_speed,
+ uint32_t *tx_queue_enable);
+int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr,
uint32_t init,
+ uint32_t queue);
+int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t
*busy);
+int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr,
uint32_t init,
+ uint32_t queue);
+int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t
*busy);
+int set_rx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue);
+int get_rx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t
*busy);
+int set_tx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue);
+int get_tx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t
*busy);
+int set_rx_ptr_queue(nthw_dbs_t *p, uint32_t queue);
+int get_rx_ptr(nthw_dbs_t *p, uint32_t *ptr, uint32_t *queue, uint32_t *valid);
+int set_tx_ptr_queue(nthw_dbs_t *p, uint32_t queue);
+int get_tx_ptr(nthw_dbs_t *p, uint32_t *ptr, uint32_t *queue, uint32_t *valid);
+int set_rx_am_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t enable,
+ uint32_t host_id,
+ uint32_t packed,
+ uint32_t int_enable);
+int set_tx_am_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t enable,
+ uint32_t host_id,
+ uint32_t packed,
+ uint32_t int_enable);
+int set_rx_uw_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t host_id,
+ uint32_t queue_size,
+ uint32_t packed,
+ uint32_t int_enable,
+ uint32_t vec,
+ uint32_t istk);
+int set_tx_uw_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t host_id,
+ uint32_t queue_size,
+ uint32_t packed,
+ uint32_t int_enable,
+ uint32_t vec,
+ uint32_t istk,
+ uint32_t in_order);
+int set_rx_dr_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t host_id,
+ uint32_t queue_size,
+ uint32_t header,
+ uint32_t packed);
+int set_tx_dr_data(nthw_dbs_t *p,
+ uint32_t index,
+ uint64_t guest_physical_address,
+ uint32_t host_id,
+ uint32_t queue_size,
+ uint32_t port,
+ uint32_t header,
+ uint32_t packed);
+int nthw_dbs_set_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t
virtual_port);
+int set_tx_qos_data(nthw_dbs_t *p, uint32_t index, uint32_t enable, uint32_t
ir, uint32_t bs);
+int set_tx_qos_rate(nthw_dbs_t *p, uint32_t mul, uint32_t div);
+
+#endif /* _NTNIC_DBS_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_nim.h
b/drivers/net/ntnic/include/ntnic_nim.h
new file mode 100644
index 0000000000..41457b7a07
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_nim.h
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef _NTNIC_NIM_H_
+#define _NTNIC_NIM_H_
+
+#include <stdint.h>
+
+typedef enum i2c_type {
+ I2C_HWIIC,
+ I2C_HWAGX
+} i2c_type_e;
+
+/*
+ * Port types
+ * The use of all non-generic XX_NOT_PRESENT is deprecated - use
+ * NT_PORT_TYPE_NIM_NOT_PRESENT instead
+ */
+enum nt_port_type_e {
+ NT_PORT_TYPE_NOT_AVAILABLE = 0, /* The NIM/port type is not available
(unknown) */
+ NT_PORT_TYPE_NOT_RECOGNISED, /* The NIM/port type not recognized */
+ NT_PORT_TYPE_RJ45, /* RJ45 type */
+ NT_PORT_TYPE_SFP_NOT_PRESENT, /* SFP type but slot is empty */
+ NT_PORT_TYPE_SFP_SX, /* SFP SX */
+ NT_PORT_TYPE_SFP_SX_DD, /* SFP SX digital diagnostic */
+ NT_PORT_TYPE_SFP_LX, /* SFP LX */
+ NT_PORT_TYPE_SFP_LX_DD, /* SFP LX digital diagnostic */
+ NT_PORT_TYPE_SFP_ZX, /* SFP ZX */
+ NT_PORT_TYPE_SFP_ZX_DD, /* SFP ZX digital diagnostic */
+ NT_PORT_TYPE_SFP_CU, /* SFP copper */
+ NT_PORT_TYPE_SFP_CU_DD, /* SFP copper digital diagnostic */
+ NT_PORT_TYPE_SFP_NOT_RECOGNISED,/* SFP unknown */
+ NT_PORT_TYPE_XFP, /* XFP */
+ NT_PORT_TYPE_XPAK, /* XPAK */
+ NT_PORT_TYPE_SFP_CU_TRI_SPEED, /* SFP copper tri-speed */
+ NT_PORT_TYPE_SFP_CU_TRI_SPEED_DD, /* SFP copper tri-speed digital
diagnostic */
+ NT_PORT_TYPE_SFP_PLUS, /* SFP+ type */
+ NT_PORT_TYPE_SFP_PLUS_NOT_PRESENT, /* SFP+ type but slot is empty
*/
+ NT_PORT_TYPE_XFP_NOT_PRESENT, /* XFP type but slot is empty */
+ NT_PORT_TYPE_QSFP_PLUS_NOT_PRESENT, /* QSFP type but slot is empty
*/
+ NT_PORT_TYPE_QSFP_PLUS, /* QSFP type */
+ NT_PORT_TYPE_SFP_PLUS_PASSIVE_DAC, /* SFP+ Passive DAC */
+ NT_PORT_TYPE_SFP_PLUS_ACTIVE_DAC, /* SFP+ Active DAC */
+ NT_PORT_TYPE_CFP4, /* CFP4 type */
+ NT_PORT_TYPE_CFP4_LR4 = NT_PORT_TYPE_CFP4, /* CFP4 100G, LR4 type
*/
+ NT_PORT_TYPE_CFP4_NOT_PRESENT, /* CFP4 type but slot is empty */
+ NT_PORT_TYPE_INITIALIZE,/* The port type is not fully established yet */
+ NT_PORT_TYPE_NIM_NOT_PRESENT, /* Generic "Not present" */
+ NT_PORT_TYPE_HCB, /* Test mode: Host Compliance Board */
+ NT_PORT_TYPE_NOT_SUPPORTED, /* The NIM type is not supported in
this context */
+ NT_PORT_TYPE_SFP_PLUS_DUAL_RATE,/* SFP+ supports 1G/10G */
+ NT_PORT_TYPE_CFP4_SR4, /* CFP4 100G, SR4 type */
+ NT_PORT_TYPE_QSFP28_NOT_PRESENT,/* QSFP28 type but slot is empty */
+ NT_PORT_TYPE_QSFP28, /* QSFP28 type */
+ NT_PORT_TYPE_QSFP28_SR4,/* QSFP28-SR4 type */
+ NT_PORT_TYPE_QSFP28_LR4,/* QSFP28-LR4 type */
+ /* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+ NT_PORT_TYPE_QSFP_PLUS_4X10,
+ /* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+ NT_PORT_TYPE_QSFP_PASSIVE_DAC_4X10,
+ /* QSFP passive DAC type */
+ NT_PORT_TYPE_QSFP_PASSIVE_DAC = NT_PORT_TYPE_QSFP_PASSIVE_DAC_4X10,
+ /* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+ NT_PORT_TYPE_QSFP_ACTIVE_DAC_4X10,
+ /* QSFP active DAC type */
+ NT_PORT_TYPE_QSFP_ACTIVE_DAC = NT_PORT_TYPE_QSFP_ACTIVE_DAC_4X10,
+ NT_PORT_TYPE_SFP_28, /* SFP28 type */
+ NT_PORT_TYPE_SFP_28_SR, /* SFP28-SR type */
+ NT_PORT_TYPE_SFP_28_LR, /* SFP28-LR type */
+ NT_PORT_TYPE_SFP_28_CR_CA_L, /* SFP28-CR-CA-L type */
+ NT_PORT_TYPE_SFP_28_CR_CA_S, /* SFP28-CR-CA-S type */
+ NT_PORT_TYPE_SFP_28_CR_CA_N, /* SFP28-CR-CA-N type */
+ NT_PORT_TYPE_QSFP28_CR_CA_L, /* QSFP28-CR-CA-L type */
+ NT_PORT_TYPE_QSFP28_CR_CA_S, /* QSFP28-CR-CA-S type */
+ NT_PORT_TYPE_QSFP28_CR_CA_N, /* QSFP28-CR-CA-N type */
+ NT_PORT_TYPE_SFP_28_SR_DR, /* SFP28-SR-DR type */
+ NT_PORT_TYPE_SFP_28_LR_DR, /* SFP28-LR-DR type */
+ NT_PORT_TYPE_SFP_FX, /* SFP FX */
+ NT_PORT_TYPE_SFP_PLUS_CU, /* SFP+ CU type */
+ /* QSFP28-FR type. Uses PAM4 modulation on one lane only */
+ NT_PORT_TYPE_QSFP28_FR,
+ /* QSFP28-DR type. Uses PAM4 modulation on one lane only */
+ NT_PORT_TYPE_QSFP28_DR,
+ /* QSFP28-LR type. Uses PAM4 modulation on one lane only */
+ NT_PORT_TYPE_QSFP28_LR,
+};
+
+typedef enum nt_port_type_e nt_port_type_t, *nt_port_type_p;
+
+typedef struct nim_i2c_ctx {
+ union {
+ nthw_iic_t hwiic; /* depends on *Fpga_t, instance number,
and cycle time */
+ struct {
+ int mux_channel;
+ } hwagx;
+ };
+ i2c_type_e type;/* 0 = hwiic (xilinx) - 1 = hwagx (agilex) */
+ uint8_t instance;
+ uint8_t devaddr;
+ uint8_t regaddr;
+ uint8_t nim_id;
+ nt_port_type_t port_type;
+
+ char vendor_name[17];
+ char prod_no[17];
+ char serial_no[17];
+ char date[9];
+ char rev[5];
+ bool avg_pwr;
+ bool content_valid;
+ uint8_t pwr_level_req;
+ uint8_t pwr_level_cur;
+ uint16_t len_info[5];
+ uint32_t speed_mask; /* Speeds supported by the NIM */
+ int8_t lane_idx;/* Is this associated with a single lane or all lanes
(-1) */
+ uint8_t lane_count;
+ uint32_t options;
+ bool tx_disable;
+ bool dmi_supp;
+
+ union {
+ struct {
+ bool sfp28;
+ bool sfpplus;
+ bool dual_rate;
+ bool hw_rate_sel;
+ bool sw_rate_sel;
+ bool cu_type;
+ bool tri_speed;
+ bool ext_cal;
+ bool addr_chg;
+ } sfp;
+
+ struct {
+ bool rx_only;
+ bool qsfp28;
+ union {
+ struct {
+ uint8_t rev_compliance;
+ bool media_side_fec_ctrl;
+ bool host_side_fec_ctrl;
+ bool media_side_fec_ena;
+ bool host_side_fec_ena;
+ } qsfp28;
+ } specific_u;
+ } qsfp;
+
+ } specific_u;
+} nim_i2c_ctx_t, *nim_i2c_ctx_p;
+
+struct nim_sensor_group {
+ struct nt_adapter_sensor *sensor;
+ void (*read)(struct nim_sensor_group *sg, nthw_spis_t *t_spi);
+ struct nim_i2c_ctx *ctx;
+ struct nim_sensor_group *next;
+};
+
+#endif /* _NTNIC_NIM_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
new file mode 100644
index 0000000000..8b7ebdf1fd
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
@@ -0,0 +1,82 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef __NTNIC_NTHW_FPGA_RST_NT200A0X_H__
+#define __NTNIC_NTHW_FPGA_RST_NT200A0X_H__
+
+#include "nthw_drv.h"
+#include "nthw_fpga_model.h"
+
+struct nthw_fpga_rst_nt200a0x {
+ int mn_fpga_product_id;
+ int mn_fpga_version;
+ int mn_fpga_revision;
+
+ int mn_hw_id;
+
+ int mn_si_labs_clock_synth_model;
+ uint8_t mn_si_labs_clock_synth_i2c_addr;
+
+ nthw_field_t *mp_fld_rst_sys;
+ nthw_field_t *mp_fld_rst_sys_mmcm;
+ nthw_field_t *mp_fld_rst_core_mmcm;
+ nthw_field_t *mp_fld_rst_rpp;
+ nthw_field_t *mp_fld_rst_ddr4;
+ nthw_field_t *mp_fld_rst_sdc;
+ nthw_field_t *mp_fld_rst_phy;
+ nthw_field_t *mp_fld_rst_serdes_rx;
+ nthw_field_t *mp_fld_rst_serdes_tx;
+ nthw_field_t *mp_fld_rst_serdes_rx_datapath;
+ nthw_field_t *mp_fld_rst_pcs_rx;
+ nthw_field_t *mp_fld_rst_mac_rx;
+ nthw_field_t *mp_fld_rst_mac_tx;
+ nthw_field_t *mp_fld_rst_ptp;
+ nthw_field_t *mp_fld_rst_ts;
+ nthw_field_t *mp_fld_rst_ptp_mmcm;
+ nthw_field_t *mp_fld_rst_ts_mmcm;
+ nthw_field_t *mp_fld_rst_periph;
+ nthw_field_t *mp_fld_rst_tsm_ref_mmcm;
+ nthw_field_t *mp_fld_rst_tmc;
+
+ /* CTRL register field pointers */
+ nthw_field_t *mp_fld_ctrl_ts_clk_sel_override;
+ nthw_field_t *mp_fld_ctrl_ts_clk_sel;
+ nthw_field_t *mp_fld_ctrl_ts_clk_sel_ref;
+ nthw_field_t *mp_fld_ctrl_ptp_mmcm_clk_sel;
+
+ /* STAT register field pointers */
+ nthw_field_t *mp_fld_stat_ddr4_mmcm_locked;
+ nthw_field_t *mp_fld_stat_sys_mmcm_locked;
+ nthw_field_t *mp_fld_stat_core_mmcm_locked;
+ nthw_field_t *mp_fld_stat_ddr4_pll_locked;
+ nthw_field_t *mp_fld_stat_ptp_mmcm_locked;
+ nthw_field_t *mp_fld_stat_ts_mmcm_locked;
+ nthw_field_t *mp_fld_stat_tsm_ref_mmcm_locked;
+
+ /* STICKY register field pointers */
+ nthw_field_t *mp_fld_sticky_ptp_mmcm_unlocked;
+ nthw_field_t *mp_fld_sticky_ts_mmcm_unlocked;
+ nthw_field_t *mp_fld_sticky_ddr4_mmcm_unlocked;
+ nthw_field_t *mp_fld_sticky_ddr4_pll_unlocked;
+ nthw_field_t *mp_fld_sticky_core_mmcm_unlocked;
+ nthw_field_t *mp_fld_sticky_pci_sys_mmcm_unlocked;
+ nthw_field_t *mp_fld_sticky_tsm_ref_mmcm_unlocked;
+
+ /* POWER register field pointers */
+ nthw_field_t *mp_fld_power_pu_phy;
+ nthw_field_t *mp_fld_power_pu_nseb;
+
+ void (*reset_serdes_rx)(struct nthw_fpga_rst_nt200a0x *p, uint32_t
intf_no, uint32_t rst);
+ void (*pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no,
uint32_t rst);
+ void (*get_serdes_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t
intf_no,
+ uint32_t *p_set);
+ void (*get_pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t
intf_no,
+ uint32_t *p_set);
+ bool (*is_rst_serdes_rx_datapath_implemented)(struct
nthw_fpga_rst_nt200a0x *p);
+};
+
+typedef struct nthw_fpga_rst_nt200a0x nthw_fpga_rst_nt200a0x_t;
+
+#endif /* __NTHW_FPGA_RST_NT200A0X_H__ */
diff --git a/drivers/net/ntnic/include/ntnic_sensor.h
b/drivers/net/ntnic/include/ntnic_sensor.h
new file mode 100644
index 0000000000..55ac519f42
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_sensor.h
@@ -0,0 +1,515 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_SENSOR_H_
+#define _NTNIC_SENSOR_H_
+
+#include "nthw_fpga_model.h"
+#include "nthw_spis.h"
+
+#define SENSOR_MON_UINT16_NAN 0xFFFF /* Most positive number used as NaN */
+#define SENSOR_MON_INT16_NAN ((int16_t)0x8000) /* Most negative number used as
NaN */
+
+/*
+ * Sensor types
+ */
+
+#pragma pack(1)
+struct sensor_mon_setup_data16 {
+ uint8_t fpga_idx; /* Destination of results */
+ uint8_t device; /* Device to monitor */
+ uint8_t device_register;/* Sensor within device */
+ uint16_t mask; /* Indicates active bits */
+ uint8_t pos; /* Position of first active bit */
+ uint16_t format;/* b0,1:sensor_mon_endian_t endian */
+ /* b2,3:sensor_mon_sign_t sign */
+ union {
+ struct {
+ int16_t limit_low; /* Signed alarm limit low */
+ int16_t limit_high; /* Signed alarm limit high */
+ } int16;
+
+ struct {
+ uint16_t limit_low; /* Unsigned alarm limit low */
+ uint16_t limit_high; /* Unsigned alarm limit high */
+ } uint16;
+ };
+};
+#pragma pack()
+struct sensor_mon_setup16 {
+ uint8_t setup_cnt; /* Number of entries in setup_data */
+ struct sensor_mon_setup_data16 setup_data[40];
+};
+
+enum nt_sensor_type_e {
+ NT_SENSOR_TYPE_UNKNOWN = 0,
+ NT_SENSOR_TYPE_TEMPERATURE = 1, /* Unit: 0.1 degree Celsius */
+ NT_SENSOR_TYPE_VOLTAGE = 2, /* Unit: 1 mV */
+ NT_SENSOR_TYPE_CURRENT = 3, /* Unit: 1 uA */
+ NT_SENSOR_TYPE_POWER = 4, /* Unit: 0.1 uW */
+ NT_SENSOR_TYPE_FAN = 5, /* Unit: 1 RPM (Revolutions Per Minute) */
+ NT_SENSOR_TYPE_HIGH_POWER = 6, /* Unit: 1 mW */
+ NT_SENSOR_TYPE_NUMBER = 7,
+};
+
+typedef enum nt_sensor_type_e nt_sensor_type_t;
+
+/*
+ * Generic SFP/SFP+/SFP28 sensors
+ *
+ * These sensors should be used instead of all adapter specific SFP sensors
+ * that have been deprecated..
+ */
+enum nt_sensors_sfp {
+ NT_SENSOR_SFP_TEMP,
+ NT_SENSOR_SFP_SUPPLY,
+ NT_SENSOR_SFP_TX_BIAS,
+ NT_SENSOR_SFP_TX_POWER,
+ NT_SENSOR_SFP_RX_POWER,
+};
+
+/*
+ * Generic QSFP/QSFP+/QSFP28 sensors
+ *
+ * These sensors should be used instead of all adapter specific QSFP sensors
+ * that have been deprecated..
+ */
+enum nt_sensors_qsfp {
+ NT_SENSOR_QSFP_TEMP,
+ NT_SENSOR_QSFP_SUPPLY,
+ NT_SENSOR_QSFP_TX_BIAS1,
+ NT_SENSOR_QSFP_TX_BIAS2,
+ NT_SENSOR_QSFP_TX_BIAS3,
+ NT_SENSOR_QSFP_TX_BIAS4,
+ NT_SENSOR_QSFP_TX_POWER1,
+ NT_SENSOR_QSFP_TX_POWER2,
+ NT_SENSOR_QSFP_TX_POWER3,
+ NT_SENSOR_QSFP_TX_POWER4,
+ NT_SENSOR_QSFP_RX_POWER1,
+ NT_SENSOR_QSFP_RX_POWER2,
+ NT_SENSOR_QSFP_RX_POWER3,
+ NT_SENSOR_QSFP_RX_POWER4,
+};
+
+/*
+ * Sensor subtypes
+ */
+enum nt_sensor_sub_type_e {
+ NT_SENSOR_SUBTYPE_NA = 0,
+ /*
+ * Subtype for NT_SENSOR_TYPE_POWER type on optical modules
+ * (optical modulation amplitude measured)
+ */
+ NT_SENSOR_SUBTYPE_POWER_OMA,
+ /* Subtype for NT_SENSOR_TYPE_POWER type on optical modules (average
power measured) */
+ NT_SENSOR_SUBTYPE_POWER_AVERAGE,
+ /* Subtype for NT_SENSOR_TYPE_HIGH_POWER type on adapters (total power
consumption) */
+ NT_SENSOR_SUBTYPE_POWER_TOTAL
+};
+
+typedef enum nt_sensor_sub_type_e nt_sensor_sub_type_t;
+
+/*
+ * Sensor source
+ */
+enum nt_sensor_source_e {
+ NT_SENSOR_SOURCE_UNKNOWN = 0x00,/* Unknown source */
+ /* Sensors located in a port. These are primary sensors - usually NIM
temperature.
+ * Presence depends on adapter and NIM type.
+ */
+ NT_SENSOR_SOURCE_PORT = 0x01,
+ /*
+ * Level 1 sensors located in a port.
+ * These are secondary sensors - usually NIM supply voltage,
+ * Tx bias and Rx/Tx optical power. Presence depends on adapter and NIM
type.
+ */
+ NT_SENSOR_SOURCE_LEVEL1_PORT = 0x02,
+#ifndef DOXYGEN_INTERNAL_ONLY
+ NT_SENSOR_SOURCE_LEVEL2_PORT = 0x04, /* Level 2 sensors located in a
port */
+#endif
+ NT_SENSOR_SOURCE_ADAPTER = 0x08,/* Sensors mounted on the adapter */
+ NT_SENSOR_SOURCE_LEVEL1_ADAPTER = 0x10, /* Level 1 sensors mounted on
the adapter */
+#ifndef DOXYGEN_INTERNAL_ONLY
+ NT_SENSOR_SOURCE_LEVEL2_ADAPTER = 0x20, /* Level 2 sensors mounted on
the adapter */
+#endif
+};
+
+/*
+ * Sensor state
+ */
+enum nt_sensor_state_e {
+ NT_SENSOR_STATE_UNKNOWN = 0, /* Unknown state */
+ NT_SENSOR_STATE_INITIALIZING = 1, /* The sensor is initializing */
+ NT_SENSOR_STATE_NORMAL = 2, /* Sensor values are within range */
+ NT_SENSOR_STATE_ALARM = 3, /* Sensor values are out of range */
+ /* The sensor is not present, for example, SFP without diagnostics */
+ NT_SENSOR_STATE_NOT_PRESENT = 4
+};
+
+typedef enum nt_sensor_state_e nt_sensor_state_t;
+
+/*
+ * Sensor value
+ */
+
+/* Indicates that sensor value or sensor limit is not valid (Not a Number) */
+#define NT_SENSOR_NAN 0x80000000
+
+enum nt_sensors_e {
+ /* Public sensors (Level 0) */
+ NT_SENSOR_FPGA_TEMP, /* FPGA temperature sensor */
+};
+
+/*
+ * Adapter types
+ */
+enum nt_adapter_type_e {
+ NT_ADAPTER_TYPE_UNKNOWN = 0, /* Unknown adapter type */
+ NT_ADAPTER_TYPE_NT4E, /* NT4E network adapter */
+ NT_ADAPTER_TYPE_NT20E, /* NT20E network adapter */
+ NT_ADAPTER_TYPE_NT4E_STD, /* NT4E-STD network adapter */
+ NT_ADAPTER_TYPE_NT4E_PORT, /* NTPORT4E expansion adapter */
+ NT_ADAPTER_TYPE_NTBPE, /* NTBPE bypass adapter */
+ NT_ADAPTER_TYPE_NT20E2, /* NT20E2 network adapter */
+ NT_ADAPTER_TYPE_RESERVED1, /* Reserved */
+ NT_ADAPTER_TYPE_RESERVED2, /* Reserved */
+ NT_ADAPTER_TYPE_NT40E2_1, /* NT40E2-1 network adapter */
+ NT_ADAPTER_TYPE_NT40E2_4, /* NT40E2-4 network adapter */
+ NT_ADAPTER_TYPE_NT4E2_4T_BP, /* NT4E2-4T-BP bypass network adapter */
+ NT_ADAPTER_TYPE_NT4E2_4_PTP, /* NT4E2-4 PTP network adapter with
IEEE1588 */
+ NT_ADAPTER_TYPE_NT20E2_PTP, /* NT20E2 PTP network adapter with
IEEE1588 */
+ NT_ADAPTER_TYPE_NT40E3_4_PTP, /* NT40E3 network adapter with IEEE1588
*/
+ NT_ADAPTER_TYPE_NT100E3_1_PTP, /* NT100E3 network adapter with
IEEE1588 */
+ NT_ADAPTER_TYPE_NT20E3_2_PTP, /* NT20E3 network adapter with IEEE1588
*/
+ NT_ADAPTER_TYPE_NT80E3_2_PTP, /* NT80E3 network adapter with IEEE1588
*/
+ NT_ADAPTER_TYPE_NT200E3_2, /* NT200E3 network adapter */
+ NT_ADAPTER_TYPE_NT200A01, /* NT200A01 network adapter */
+ /* NT200A01 2 x 100 Gbps network adapter */
+ NT_ADAPTER_TYPE_NT200A01_2X100 = NT_ADAPTER_TYPE_NT200A01,
+ NT_ADAPTER_TYPE_NT40A01_4X1, /* NT40A01_4X1 network adapter with
IEEE1588 */
+ NT_ADAPTER_TYPE_NT200A01_2X40, /* NT200A01 2 x 40 Gbps network adapter
*/
+ /* NT80E3 8 x 10 Gbps network adapter with IEEE1588 */
+ NT_ADAPTER_TYPE_NT80E3_2_PTP_8X10,
+ /* */
+ NT_ADAPTER_TYPE_INTEL_A10_4X10, /* Intel PAC A10 GX 4 x 10 Gbps network
adapter */
+ NT_ADAPTER_TYPE_INTEL_A10_1X40, /* Intel PAC A10 GX 1 x 40 Gbps network
adapter */
+ /* */
+ NT_ADAPTER_TYPE_NT200A01_8X10, /* NT200A01 8 x 10 Gbps network adapter
*/
+ NT_ADAPTER_TYPE_NT200A02_2X100, /* NT200A02 2 x 100 Gbps network
adapter */
+ NT_ADAPTER_TYPE_NT200A02_2X40, /* NT200A02 2 x 40 Gbps network adapter
*/
+ NT_ADAPTER_TYPE_NT200A01_2X25, /* Deprecated */
+ /* NT200A01 2 x 10/25 Gbps network adapter */
+ NT_ADAPTER_TYPE_NT200A01_2X10_25 = NT_ADAPTER_TYPE_NT200A01_2X25,
+ NT_ADAPTER_TYPE_NT200A02_2X25, /* Deprecated */
+ /* NT200A02 2 x 10/25 Gbps network adapter */
+ NT_ADAPTER_TYPE_NT200A02_2X10_25 = NT_ADAPTER_TYPE_NT200A02_2X25,
+ NT_ADAPTER_TYPE_NT200A02_4X25, /* Deprecated */
+ /* NT200A02 4 x 10/25 Gbps network adapter */
+ NT_ADAPTER_TYPE_NT200A02_4X10_25 = NT_ADAPTER_TYPE_NT200A02_4X25,
+ NT_ADAPTER_TYPE_NT200A02_8X10, /* NT200A02 8 x 10 Gbps network adapter
*/
+ NT_ADAPTER_TYPE_NT50B01_2X25, /* Deprecated */
+ /* NT50B01 2 x 10/25 Gbps network adapter */
+ NT_ADAPTER_TYPE_NT50B01_2X10_25 = NT_ADAPTER_TYPE_NT50B01_2X25,
+ NT_ADAPTER_TYPE_NT200A02_2X1_10,/* NT200A02 2 x 1/10 Gbps network
adapter */
+ NT_ADAPTER_TYPE_NT100A01_4X1_10,/* NT100A01 4 x 1/10 Gbps network
adapter */
+ NT_ADAPTER_TYPE_NT100A01_4X10_25, /* NT100A01 4 x 10/25 Gbps
network adapter */
+ NT_ADAPTER_TYPE_NT50B01_2X1_10, /* NT50B01 2 x 1/10 Gbps network
adapter */
+ NT_ADAPTER_TYPE_NT40A11_4X1_10, /* NT40A11 4 x 1/10 Gbps network
adapter */
+ NT_ADAPTER_TYPE_NT400D11_2X100, /*!< NT400D11 2 x 100 Gbps network
adapter */
+#ifndef DOXYGEN_INTERNAL_ONLY
+ NT_ADAPTER_TYPE_ML605 = 10000, /* NT20E2 eval board */
+#endif
+ NT_ADAPTER_TYPE_4GARCH_HAMOA =
+ (1U << 29), /* Bit to mark to adapters as a 4GArch Hamoa
adapter */
+ NT_ADAPTER_TYPE_4GARCH = (1U << 30), /* Bit to mark to adapters as a
4GArch adapter */
+ /* NOTE: do *NOT* add normal adapters after the group bit mark enums */
+};
+
+/* The NT200E3 adapter sensor id's */
+typedef enum nt_sensors_adapter_nt200_e3_e {
+ /* Public sensors (Level 0) */
+ NT_SENSOR_NT200E3_FPGA_TEMP, /* FPGA temperature sensor */
+ NT_SENSOR_NT200E3_FAN_SPEED, /* FAN speed sensor */
+ /* MCU (Micro Controller Unit) temperature sensor located inside
enclosure below FAN */
+ NT_SENSOR_NT200E3_MCU_TEMP,
+ NT_SENSOR_NT200E3_PSU0_TEMP, /* Power supply 0 temperature sensor */
+ NT_SENSOR_NT200E3_PSU1_TEMP, /* Power supply 1 temperature sensor */
+ NT_SENSOR_NT200E3_PCB_TEMP, /* PCB temperature sensor */
+
+ /* Diagnostic sensors (Level 1) */
+ /* Total power consumption (calculated value) - does not generate
alarms */
+ NT_SENSOR_NT200E3_NT200E3_POWER,
+ /* FPGA power consumption (calculated value) - does not generate alarms
*/
+ NT_SENSOR_NT200E3_FPGA_POWER,
+ /* DDR4 RAM power consumption (calculated value) - does not generate
alarms */
+ NT_SENSOR_NT200E3_DDR4_POWER,
+ /* NIM power consumption (calculated value) - does not generate alarms
*/
+ NT_SENSOR_NT200E3_NIM_POWER,
+
+ NT_SENSOR_NT200E3_L1_MAX, /* Number of NT200E3 level 0,1 board
sensors */
+} nt_sensors_adapter_nt200_e3_t;
+
+/* The following sensors are deprecated - generic types should be used instead
*/
+/* The NIM temperature sensor must be the one with the lowest sensor_index */
+/* (enum value) in order to be shown by the monitoring tool in port mode */
+enum nt_sensors_port_nt200_e3_2_e {
+ /* Public sensors */
+ NT_SENSOR_NT200E3_NIM, /* QSFP28 temperature sensor */
+
+ /* Diagnostic sensors (Level 1) */
+ NT_SENSOR_NT200E3_SUPPLY, /* QSFP28 supply voltage sensor */
+ NT_SENSOR_NT200E3_TX_BIAS1, /* QSFP28 TX bias line 0 current sensor
*/
+ NT_SENSOR_NT200E3_TX_BIAS2, /* QSFP28 TX bias line 1 current sensor
*/
+ NT_SENSOR_NT200E3_TX_BIAS3, /* QSFP28 TX bias line 2 current sensor
*/
+ NT_SENSOR_NT200E3_TX_BIAS4, /* QSFP28 TX bias line 3 current sensor
*/
+ NT_SENSOR_NT200E3_RX1, /* QSFP28 RX line 0 power sensor */
+ NT_SENSOR_NT200E3_RX2, /* QSFP28 RX line 1 power sensor */
+ NT_SENSOR_NT200E3_RX3, /* QSFP28 RX line 2 power sensor */
+ NT_SENSOR_NT200E3_RX4, /* QSFP28 RX line 3 power sensor */
+ NT_SENSOR_NT200E3_TX1, /* QSFP28 TX line 0 power sensor */
+ NT_SENSOR_NT200E3_TX2, /* QSFP28 TX line 1 power sensor */
+ NT_SENSOR_NT200E3_TX3, /* QSFP28 TX line 2 power sensor */
+ NT_SENSOR_NT200E3_TX4, /* QSFP28 TX line 3 power sensor */
+ NT_SENSOR_NT200E3_PORT_MAX, /* Number of NT200E3 port sensors */
+};
+
+typedef enum nt_sensors_adapter_nt400d11_e {
+ /*
+ * Public sensors (Level 0)
+ * NT_SENSOR_NT400D11_FPGA_TEMP, //!< FPGA temperature
sensor
+ */
+ /* !< FPGA temperature sensor 2 = NT_SENSOR_NT400D11_FPGA_TEMP */
+ NT_SENSOR_NT400D11_TEMP2_TEMP_CORE_FABRIC,
+ NT_SENSOR_NT400D11_FAN_SPEED, /* !< FAN speed sensor */
+ /* !< MCU (Micro Controller Unit) temperature sensor located inside
enclosure below FAN */
+ NT_SENSOR_NT400D11_MCU_TEMP,
+ NT_SENSOR_NT400D11_PSU1_TEMP, /* !< Power supply 1 temperature sensor
*/
+ NT_SENSOR_NT400D11_PSU2_TEMP, /* !< Power supply 2 temperature sensor
*/
+ NT_SENSOR_NT400D11_PSU3_TEMP, /* !< Power supply 3 temperature sensor
*/
+ NT_SENSOR_NT400D11_PSU5_TEMP, /* !< Power supply 5 temperature sensor
*/
+ NT_SENSOR_NT400D11_L1_MAX, /* !< Number of NT400D11 level 0,1
board sensors */
+} nt_sensors_adapter_nt400_d11_t;
+
+typedef enum nt_sensors_adapter_nt400_d11_level2_t {
+ /* Supportinfo sensors (Level 2) */
+ /* !< FPGA temperature sensor 1 */
+ NT_SENSOR_NT400D11_TEMP3_TEMP_INLET = NT_SENSOR_NT400D11_L1_MAX,
+ NT_SENSOR_NT400D11_L2_MAX
+} nt_sensors_adapter_nt400_d11_level2_t;
+
+enum nt_sensor_event_alarm_e {
+ NT_SENSOR_ENABLE_ALARM,
+ NT_SENSOR_LOG_ALARM,
+ NT_SENSOR_DISABLE_ALARM,
+};
+
+/*
+ * Specify the nature of the raw data. AVR and ntservice must use this
+ * information when comparing or converting to native format which is little
endian
+ */
+enum sensor_mon_endian {
+ SENSOR_MON_LITTLE_ENDIAN,
+ SENSOR_MON_BIG_ENDIAN
+};
+
+enum sensor_mon_sign {
+ SENSOR_MON_UNSIGNED,
+ SENSOR_MON_SIGNED, /* 2's complement */
+};
+
+/* Define sensor devices */
+enum sensor_mon_device {
+ SENSOR_MON_PSU_EXAR_7724_0 = 0, /* NT40E3, NT100E3 */
+ SENSOR_MON_PSU_EXAR_7724_1, /* NT40E3, NT100E3 */
+ SENSOR_MON_PSU_LTM_4676_0, /* na NT100E3, page-0 */
+ SENSOR_MON_PSU_LTM_4676_1, /* na NT100E3, page-0 */
+ SENSOR_MON_INA219_1, /* NT40E3, NT100E3 */
+ SENSOR_MON_INA219_2, /* NT40E3, NT100E3 */
+ SENSOR_MON_MAX6642, /* NT40E3, NT100E3 */
+ SENSOR_MON_DS1775, /* NT40E3, NT100E3 */
+ SENSOR_MON_FAN, /* NT40E3, NT100E3 */
+ SENSOR_MON_AVR, /* NT40E3, NT100E3 */
+ SENSOR_MON_PEX8734, /* na NT100E3 */
+ SENSOR_MON_RATE_COUNT, /* NT40E3, NT100E3 */
+ SENSOR_MON_PSU_LTM_4676_0_1, /* na NT100E3, page-1 */
+ SENSOR_MON_PSU_LTM_4676_1_1, /* na NT100E3, page-1 */
+ SENSOR_MON_MP2886A, /* na, na, NT200A02, */
+ SENSOR_MON_PSU_EM2260_1,/* na, na, na, na,
NT200D01^M */
+ SENSOR_MON_PSU_EM2120_2,/* na, na, na, na,
NT200D01^M */
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP2886A_PSU_1,
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP8869S_PSU_2,
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP8645PGVT_PSU_3,
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP8645PGVT_PSU_4,
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP8869S_PSU_5,
+ /* na, na, na, NT200A02, na, NT50B01, */
+ SENSOR_MON_MP8869S_PSU_6,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8869S_PSU_1,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8645PGVT_PSU_2,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8869S_PSU_4,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8869S_PSU_6,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8869S_PSU_7,
+ /* NT40E3, na, na, na, na, na, na */
+ SENSOR_MON_NT40E3_MP8869S_PSU_8,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_1,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_2_PAGE_0,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_3,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_4,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_5,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_6,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_TMP464_1,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_TMP464_2,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_INA3221,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_MPS_PSU_2_PAGE_1,
+ /* na, na, na, na, na, na, na,
NT400D11 */
+ SENSOR_MON_DEVICE_COUNT
+};
+
+/* Define sensor monitoring control */
+enum sensor_mon_control {
+ SENSOR_MON_CTRL_STOP = 0, /* Stop sensor monitoring */
+ SENSOR_MON_CTRL_RUN = 1,/* Start sensor monitoring */
+ SENSOR_MON_CTRL_REM_ALL_SENSORS = 2, /* Stop and remove all sensor
monitoring setup */
+};
+
+/*
+ * This structure will return the sensor specific information
+ *
+ * The units used for the fields: value, value_lowest, value_highest,
limit_low and
+ * limit_high depend on the type field. See @ref NtSensorType_e.
+ *
+ * For the limit_low and limit_high fields the following applies:\n
+ * If the sensor is located in a NIM (Network Interface Module), the limits
are read
+ * from the NIM module via the DMI (Diagnostic Monitoring Interface) from the
alarm
+ * and warning thresholds section, and the units are changed to internal
representation.
+ * Only the alarm thresholds are used and are read only once during
initialization.
+ * The limits cannot be changed.
+ *
+ * The value field is updated internally on a regular basis and is also based
on a
+ * value read from the NIM which is also changed to internal representation.
+ *
+ * Not all NIM types support DMI data, and its presence must be determined by
reading an
+ * option flag. In general, a NIM can read out: temperature, supply voltage,
+ * TX bias, TX optical power and RX optical power but not all NIM types
support all
+ * 5 values.
+ *
+ * If external calibration is used (most NIM use internal calibration), both
the
+ * current value and the threshold values are subjected to the specified
calibration
+ * along with the change to internal calibration.
+ */
+#define NT_INFO_SENSOR_NAME 50
+struct nt_info_sensor_s {
+ /* The source of the sensor (port or adapter on which the sensor
resides) */
+ enum nt_sensor_source_e source;
+ /*
+ * The source index - the adapter number for
+ * adapter sensors and port number for port sensors
+ */
+ uint32_t source_index;
+ /*
+ * The sensor index within the source index
+ * (sensor number on the adapter or sensor number on the port)
+ */
+ uint32_t sensor_index;
+ enum nt_sensor_type_e type; /* The sensor type */
+ enum nt_sensor_sub_type_e subtype; /* The sensor subtype (if
applicable) */
+ enum nt_sensor_state_e state; /* The current state (normal or alarm)
*/
+ int32_t value; /* The current value */
+ int32_t value_lowest; /* The lowest value registered */
+ int32_t value_highest; /* The highest value registered */
+ char name[NT_INFO_SENSOR_NAME + 1]; /* The sensor name */
+ enum nt_adapter_type_e adaptertype; /* The adapter type where the
sensor resides */
+};
+
+/*
+ * Port of the sensor class
+ */
+struct nt_adapter_sensor {
+ uint8_t m_adapter_no;
+ uint8_t m_intf_no;
+ uint8_t fpga_idx; /* for AVR sensors */
+ enum sensor_mon_sign si;
+ struct nt_info_sensor_s info;
+ enum nt_sensor_event_alarm_e alarm;
+ bool m_enable_alarm;
+};
+
+struct nt_fpga_sensor_monitor {
+ nthw_fpga_t *FPGA;
+ nthw_module_t *mod;
+
+ nthw_register_t *reg;
+ nthw_field_t **fields;
+ uint8_t fields_num;
+};
+
+/*
+ * Sensor description.
+ * Describe the static behavior of the sensor.
+ */
+struct nt_adapter_sensor_description {
+ enum nt_sensor_type_e type; /* Sensor type. */
+ enum nt_sensor_sub_type_e subtype; /* Sensor subtype (if any
applicable) */
+ unsigned int index; /* Sensor group index. */
+ enum nt_sensor_event_alarm_e event_alarm; /* Enable/Disable event
alarm */
+ char name[20]; /* Sensor name. */
+};
+
+struct nt_sensor_group {
+ struct nt_adapter_sensor *sensor;
+ struct nt_fpga_sensor_monitor *monitor;
+ void (*read)(struct nt_sensor_group *sg, nthw_spis_t *t_spi);
+
+ /* conv params are needed to call current conversion functions */
+ int (*conv_func)(uint32_t p_sensor_result);
+ /* i2c interface for NIM sensors */
+
+ struct nt_sensor_group *next;
+};
+
+/* The NT200A02 adapter sensor id's */
+enum nt_sensors_adapter_nt200a02_e {
+ /* Public sensors (Level 0) */
+ NT_SENSOR_NT200A02_FPGA_TEMP, /* FPGA temperature sensor */
+ NT_SENSOR_NT200A02_FAN_SPEED, /* FAN speed sensor */
+ /* MCU (Micro Controller Unit) temperature sensor located inside
enclosure below FAN */
+ NT_SENSOR_NT200A02_MCU_TEMP,
+ NT_SENSOR_NT200A02_PSU0_TEMP, /* Power supply 0 temperature sensor */
+ NT_SENSOR_NT200A02_PSU1_TEMP, /* Power supply 1 temperature sensor */
+ NT_SENSOR_NT200A02_PCB_TEMP, /* PCB temperature sensor */
+
+ /* Diagnostic sensors (Level 1) */
+ /* Total power consumption (calculated value) - does not generate
alarms */
+ NT_SENSOR_NT200A02_NT200A02_POWER,
+ /* FPGA power consumption (calculated value) - does not generate alarms
*/
+ NT_SENSOR_NT200A02_FPGA_POWER,
+ /* DDR4 RAM power consumption (calculated value) - does not generate
alarms */
+ NT_SENSOR_NT200A02_DDR4_POWER,
+ /* NIM power consumption (calculated value) - does not generate alarms
*/
+ NT_SENSOR_NT200A02_NIM_POWER,
+ /* Number of NT200A01 level 0,1 board sensors */
+ NT_SENSOR_NT200A02_L1_MAX,
+};
+
+#endif /* _NTNIC_SENSOR_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_stat.h
b/drivers/net/ntnic/include/ntnic_stat.h
new file mode 100644
index 0000000000..3ef5980cf5
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_stat.h
@@ -0,0 +1,291 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTNIC_STAT_H_
+#define NTNIC_STAT_H_
+
+#include "common_adapter_defs.h"
+#include "nthw_fpga_model.h"
+
+#define NT_MAX_COLOR_FLOW_STATS 0x400
+
+struct nthw_stat {
+ nthw_fpga_t *mp_fpga;
+ nthw_module_t *mp_mod_stat;
+ int mn_instance;
+
+ int mn_stat_layout_version;
+
+ bool mb_is_vswitch;
+ bool mb_has_tx_stats;
+
+ int m_nb_phy_ports;
+ int m_nb_nim_ports;
+
+ int m_nb_rx_ports;
+ int m_nb_tx_ports;
+
+ int m_nb_rx_host_buffers;
+ int m_nb_tx_host_buffers;
+
+ int m_dbs_present;
+
+ int m_rx_port_replicate;
+
+ int m_nb_color_counters;
+
+ int m_nb_rx_hb_counters;
+ int m_nb_tx_hb_counters;
+
+ int m_nb_rx_port_counters;
+ int m_nb_tx_port_counters;
+
+ int m_nb_counters;
+
+ int m_nb_rpp_per_ps;
+
+ nthw_field_t *mp_fld_dma_ena;
+ nthw_field_t *mp_fld_cnt_clear;
+
+ nthw_field_t *mp_fld_tx_disable;
+
+ nthw_field_t *mp_fld_cnt_freeze;
+
+ nthw_field_t *mp_fld_stat_toggle_missed;
+
+ nthw_field_t *mp_fld_dma_lsb;
+ nthw_field_t *mp_fld_dma_msb;
+
+ nthw_field_t *mp_fld_load_bin;
+ nthw_field_t *mp_fld_load_bps_rx0;
+ nthw_field_t *mp_fld_load_bps_rx1;
+ nthw_field_t *mp_fld_load_bps_tx0;
+ nthw_field_t *mp_fld_load_bps_tx1;
+ nthw_field_t *mp_fld_load_pps_rx0;
+ nthw_field_t *mp_fld_load_pps_rx1;
+ nthw_field_t *mp_fld_load_pps_tx0;
+ nthw_field_t *mp_fld_load_pps_tx1;
+
+ uint64_t m_stat_dma_physical;
+ uint32_t *mp_stat_dma_virtual;
+
+ uint64_t last_ts;
+
+ uint64_t *mp_timestamp;
+};
+
+typedef struct nthw_stat nthw_stat_t;
+typedef struct nthw_stat nthw_stat;
+
+struct color_counters {
+ uint64_t color_packets;
+ uint64_t color_bytes;
+ uint8_t tcp_flags;
+};
+
+struct host_buffer_counters {
+ uint64_t flush_packets;
+ uint64_t drop_packets;
+ uint64_t fwd_packets;
+ uint64_t dbs_drop_packets;
+ uint64_t flush_bytes;
+ uint64_t drop_bytes;
+ uint64_t fwd_bytes;
+ uint64_t dbs_drop_bytes;
+};
+
+struct port_load_counters {
+ uint64_t rx_pps;
+ uint64_t rx_pps_max;
+ uint64_t tx_pps;
+ uint64_t tx_pps_max;
+ uint64_t rx_bps;
+ uint64_t rx_bps_max;
+ uint64_t tx_bps;
+ uint64_t tx_bps_max;
+};
+
+struct port_counters_v2 {
+ /* Rx/Tx common port counters */
+ uint64_t drop_events;
+ uint64_t pkts;
+ /* FPGA counters */
+ uint64_t octets;
+ uint64_t broadcast_pkts;
+ uint64_t multicast_pkts;
+ uint64_t unicast_pkts;
+ uint64_t pkts_alignment;
+ uint64_t pkts_code_violation;
+ uint64_t pkts_crc;
+ uint64_t undersize_pkts;
+ uint64_t oversize_pkts;
+ uint64_t fragments;
+ uint64_t jabbers_not_truncated;
+ uint64_t jabbers_truncated;
+ uint64_t pkts_64_octets;
+ uint64_t pkts_65_to_127_octets;
+ uint64_t pkts_128_to_255_octets;
+ uint64_t pkts_256_to_511_octets;
+ uint64_t pkts_512_to_1023_octets;
+ uint64_t pkts_1024_to_1518_octets;
+ uint64_t pkts_1519_to_2047_octets;
+ uint64_t pkts_2048_to_4095_octets;
+ uint64_t pkts_4096_to_8191_octets;
+ uint64_t pkts_8192_to_max_octets;
+ uint64_t mac_drop_events;
+ uint64_t pkts_lr;
+ /* Rx only port counters */
+ uint64_t duplicate;
+ uint64_t pkts_ip_chksum_error;
+ uint64_t pkts_udp_chksum_error;
+ uint64_t pkts_tcp_chksum_error;
+ uint64_t pkts_giant_undersize;
+ uint64_t pkts_baby_giant;
+ uint64_t pkts_not_isl_vlan_mpls;
+ uint64_t pkts_isl;
+ uint64_t pkts_vlan;
+ uint64_t pkts_isl_vlan;
+ uint64_t pkts_mpls;
+ uint64_t pkts_isl_mpls;
+ uint64_t pkts_vlan_mpls;
+ uint64_t pkts_isl_vlan_mpls;
+ uint64_t pkts_no_filter;
+ uint64_t pkts_dedup_drop;
+ uint64_t pkts_filter_drop;
+ uint64_t pkts_overflow;
+ uint64_t pkts_dbs_drop;
+ uint64_t octets_no_filter;
+ uint64_t octets_dedup_drop;
+ uint64_t octets_filter_drop;
+ uint64_t octets_overflow;
+ uint64_t octets_dbs_drop;
+ uint64_t ipft_first_hit;
+ uint64_t ipft_first_not_hit;
+ uint64_t ipft_mid_hit;
+ uint64_t ipft_mid_not_hit;
+ uint64_t ipft_last_hit;
+ uint64_t ipft_last_not_hit;
+};
+
+struct port_counters_vswitch_v1 {
+ /* Rx/Tx common port counters */
+ uint64_t octets;
+ uint64_t pkts;
+ uint64_t drop_events;
+ uint64_t qos_drop_octets;
+ uint64_t qos_drop_pkts;
+};
+
+struct flm_counters_v1 {
+ /* FLM 0.17 */
+ uint64_t current;
+ uint64_t learn_done;
+ uint64_t learn_ignore;
+ uint64_t learn_fail;
+ uint64_t unlearn_done;
+ uint64_t unlearn_ignore;
+ uint64_t auto_unlearn_done;
+ uint64_t auto_unlearn_ignore;
+ uint64_t auto_unlearn_fail;
+ uint64_t timeout_unlearn_done;
+ uint64_t rel_done;
+ uint64_t rel_ignore;
+ /* FLM 0.20 */
+ uint64_t prb_done;
+ uint64_t prb_ignore;
+ uint64_t sta_done;
+ uint64_t inf_done;
+ uint64_t inf_skip;
+ uint64_t pck_hit;
+ uint64_t pck_miss;
+ uint64_t pck_unh;
+ uint64_t pck_dis;
+ uint64_t csh_hit;
+ uint64_t csh_miss;
+ uint64_t csh_unh;
+ uint64_t cuc_start;
+ uint64_t cuc_move;
+ /* FLM 0.17 Load */
+ uint64_t load_lps;
+ uint64_t load_aps;
+ uint64_t max_lps;
+ uint64_t max_aps;
+};
+
+struct nt4ga_stat_s {
+ nthw_stat_t *mp_nthw_stat;
+ struct nt_dma_s *p_stat_dma;
+ uint32_t *p_stat_dma_virtual;
+ uint32_t n_stat_size;
+
+ uint64_t last_timestamp;
+
+ int mn_rx_host_buffers;
+ int mn_tx_host_buffers;
+
+ int mn_rx_ports;
+ int mn_tx_ports;
+
+ struct color_counters *mp_stat_structs_color;
+ /* For calculating increments between stats polls */
+ struct color_counters
a_stat_structs_color_base[NT_MAX_COLOR_FLOW_STATS];
+
+ union {
+ /* Port counters for VSWITCH/inline */
+ struct {
+ struct port_counters_vswitch_v1
*mp_stat_structs_port_rx;
+ struct port_counters_vswitch_v1
*mp_stat_structs_port_tx;
+ } virt;
+ struct {
+ struct port_counters_v2 *mp_stat_structs_port_rx;
+ struct port_counters_v2 *mp_stat_structs_port_tx;
+ } cap;
+ };
+
+ struct host_buffer_counters *mp_stat_structs_hb;
+ struct port_load_counters *mp_port_load;
+
+ int flm_stat_ver;
+ struct flm_counters_v1 *mp_stat_structs_flm;
+
+ /* Rx/Tx totals: */
+ uint64_t n_totals_reset_timestamp; /* timestamp for last totals
reset */
+
+ uint64_t a_port_rx_octets_total[NUM_ADAPTER_PORTS_MAX];
+ /* Base is for calculating increments between statistics reads */
+ uint64_t a_port_rx_octets_base[NUM_ADAPTER_PORTS_MAX];
+
+ uint64_t a_port_rx_packets_total[NUM_ADAPTER_PORTS_MAX];
+ uint64_t a_port_rx_packets_base[NUM_ADAPTER_PORTS_MAX];
+
+ uint64_t a_port_rx_drops_total[NUM_ADAPTER_PORTS_MAX];
+ uint64_t a_port_rx_drops_base[NUM_ADAPTER_PORTS_MAX];
+
+ uint64_t a_port_tx_octets_total[NUM_ADAPTER_PORTS_MAX];
+ uint64_t a_port_tx_octets_base[NUM_ADAPTER_PORTS_MAX];
+
+ uint64_t a_port_tx_packets_base[NUM_ADAPTER_PORTS_MAX];
+ uint64_t a_port_tx_packets_total[NUM_ADAPTER_PORTS_MAX];
+
+ uint64_t a_port_tx_drops_base[NUM_ADAPTER_PORTS_MAX];
+ uint64_t a_port_tx_drops_total[NUM_ADAPTER_PORTS_MAX];
+};
+
+typedef struct nt4ga_stat_s nt4ga_stat_t;
+
+nthw_stat_t *nthw_stat_new(void);
+int nthw_stat_init(nthw_stat_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_stat_delete(nthw_stat_t *p);
+
+int nthw_stat_set_dma_address(nthw_stat_t *p, uint64_t stat_dma_physical,
+ uint32_t *p_stat_dma_virtual);
+int nthw_stat_trigger(nthw_stat_t *p);
+
+int nthw_stat_get_load_bps_rx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_bps_tx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_pps_rx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_pps_tx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+
+#endif /* NTNIC_STAT_H_ */
--
2.45.0
