Currently, in switch mode, mlx5 PMD only supports match with
dedicate vport. There is a usercase which user may want to
offload the rules only to match with all the pkt sent by
application not from vport.
Since the port_id info of pkt sent by application is switch
manager, and kernel driver has exposed the switch manager
register value, this commit adds the support of register
matching for switch manager.
Signed-off-by: Suanming Mou <suanmi...@nvidia.com>
---
doc/guides/rel_notes/release_24_07.rst | 1 +
drivers/common/mlx5/linux/meson.build | 2 ++
drivers/net/mlx5/linux/mlx5_os.c | 12 ++++++++++++
drivers/net/mlx5/mlx5.h | 14 ++++++++++++++
drivers/net/mlx5/mlx5_flow.h | 6 ------
drivers/net/mlx5/mlx5_flow_dv.c | 24 +++++++++++++++++++-----
6 files changed, 48 insertions(+), 11 deletions(-)
diff --git a/doc/guides/rel_notes/release_24_07.rst
b/doc/guides/rel_notes/release_24_07.rst
index 46efc04eac..389178acb0 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -84,6 +84,7 @@ New Features
* **Updated NVIDIA mlx5 driver.**
* Added match with Tx queue.
+ * Added match with switch manager.
Removed Items
diff --git a/drivers/common/mlx5/linux/meson.build
b/drivers/common/mlx5/linux/meson.build
index cdee40c553..82e8046e0c 100644
--- a/drivers/common/mlx5/linux/meson.build
+++ b/drivers/common/mlx5/linux/meson.build
@@ -201,6 +201,8 @@ has_sym_args = [
'mlx5dv_create_steering_anchor'],
[ 'HAVE_IBV_FORK_UNNEEDED', 'infiniband/verbs.h',
'ibv_is_fork_initialized'],
+ [ 'HAVE_IBV_DEVICE_ATTR_ESW_MGR_REG_C0', 'infiniband/mlx5dv.h',
+ 'MLX5DV_CONTEXT_MASK_REG_C0' ],
]
if libmtcr_ul_found
has_sym_args += [
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index bb566ea236..24ea58fd01 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -160,6 +160,9 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
#endif
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
+#endif
+#ifdef HAVE_IBV_DEVICE_ATTR_ESW_MGR_REG_C0
+ dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_REG_C0;
#endif
err = mlx5_glue->dv_query_device(cdev->ctx, &dv_attr);
if (err) {
@@ -374,6 +377,15 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared
*sh)
hca_attr->scatter_fcs_w_decap_disable;
sh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop;
mlx5_rt_timestamp_config(sh, hca_attr);
+#ifdef HAVE_IBV_DEVICE_ATTR_ESW_MGR_REG_C0
+ if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_REG_C0) {
+ sh->dev_cap.esw_info.regc_value = dv_attr.reg_c0.value;
+ sh->dev_cap.esw_info.regc_mask = dv_attr.reg_c0.mask;
+ }
+#else
+ sh->dev_cap.esw_info.regc_value = 0;
+ sh->dev_cap.esw_info.regc_mask = 0;
+#endif
return 0;
}
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 5b23043b8b..13718273dc 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -141,6 +141,19 @@ struct mlx5_flow_cb_ctx {
void *data2;
};
+struct flow_hw_port_info {
+ uint32_t regc_mask;
+ uint32_t regc_value;
+ uint32_t is_wire:1;
+ uint32_t direction:2;
+};
+
+enum mlx5_vport_direction {
+ MLX5_VPORT_DIRECTION_ANY = 0,
+ MLX5_VPORT_DIRECTION_NORTH,
+ MLX5_VPORT_DIRECTION_SOUTH,
+};
+
/* Device capabilities structure which isn't changed in any stage. */
struct mlx5_dev_cap {
int max_cq; /* Maximum number of supported CQs */
@@ -184,6 +197,7 @@ struct mlx5_dev_cap {
/* Log min WQE size, (size of single stride)*(num of strides).*/
} mprq; /* Capability for Multi-Packet RQ. */
char fw_ver[64]; /* Firmware version of this device. */
+ struct flow_hw_port_info esw_info; /* E-switch manager reg_c0. */
};
#define MLX5_MPESW_PORT_INVALID (-1)
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 9a359da042..0a6d33f8ee 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1938,12 +1938,6 @@ struct mlx5_hl_data {
uint32_t dw_mask;
};
-struct flow_hw_port_info {
- uint32_t regc_mask;
- uint32_t regc_value;
- uint32_t is_wire:1;
-};
-
extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];
/*
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index a834b3e2e0..5477eba4a0 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -10837,17 +10837,31 @@ flow_dv_translate_item_represented_port(struct
rte_eth_dev *dev, void *key,
const struct rte_flow_item_ethdev *pid_m = item ? item->mask : NULL;
const struct rte_flow_item_ethdev *pid_v = item ? item->spec : NULL;
struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
- struct mlx5_priv *priv;
+ struct mlx5_priv *priv = dev->data->dev_private;
uint16_t mask, id;
uint32_t vport_meta;
+ bool vport_match = false;
MLX5_ASSERT(wks);
+#ifndef HAVE_IBV_DEVICE_ATTR_ESW_MGR_REG_C0
+ if (priv->sh->config.dv_flow_en == 2)
+ vport_match = true;
+#endif
if (!pid_m && !pid_v)
return 0;
if (pid_v && pid_v->port_id == UINT16_MAX) {
- flow_dv_translate_item_source_vport(key,
- key_type & MLX5_SET_MATCHER_V ?
- mlx5_flow_get_esw_manager_vport_id(dev) : 0xffff);
+ if (priv->sh->config.dv_flow_en != 2 || vport_match) {
+ flow_dv_translate_item_source_vport
+ (key, key_type & MLX5_SET_MATCHER_V ?
+ mlx5_flow_get_esw_manager_vport_id(dev) :
0xffff);
+ } else {
+ if (key_type & MLX5_SET_MATCHER_M)
+ vport_meta =
priv->sh->dev_cap.esw_info.regc_mask;
+ else
+ vport_meta =
priv->sh->dev_cap.esw_info.regc_value;
+ flow_dv_translate_item_meta_vport(key, vport_meta,
+
priv->sh->dev_cap.esw_info.regc_mask);
+ }
return 0;
}
mask = pid_m ? pid_m->port_id : UINT16_MAX;
@@ -10868,7 +10882,7 @@ flow_dv_translate_item_represented_port(struct
rte_eth_dev *dev, void *key,
* Kernel can use either misc.source_port or half of C0 metadata
* register.
*/
- if (priv->vport_meta_mask) {
+ if (priv->vport_meta_mask && !vport_match) {
/*
* Provide the hint for SW steering library
* to insert the flow into ingress domain and
--
2.34.1
