On Thu, May 2, 2024 at 1:16 AM Abdullah Sevincer <abdullah.sevin...@intel.com> wrote: > > In DLB 2.5, hardware assist is available, complementing the Delayed > token POP software implementation. When it is enabled, the feature > works as follows: > > It stops CQ scheduling when the inflight limit associated with the CQ > is reached. So the feature is activated only if the core is > congested. If the core can handle multiple atomic flows, DLB will not > try to switch them. This is an improvement over SW implementation > which always switches the flows. > > The feature will resume CQ scheduling when the number of pending > completions fall below a configured threshold. > > DLB has 64 LDB ports and 2048 HL entries. If all LDB ports are used, > possible HL entries per LDB port equals 2048 / 64 = 32. So, the > maximum CQ depth possible is 16, if all 64 LB ports are needed in a > high-performance setting. > > In case all CQs are configured to have HL = 2* CQ Depth as a > performance option, then the calculation of HL at the time of domain > creation will be based on maximum possible dequeue depth. This could > result in allocating too many HL entries to the domain as DLB only > has limited number of HL entries to be allocated. Hence, it is best > to allow application to specify HL entries as a command line argument > and override default allocation. A summary of usage is listed below: > > When 'use_default_hl = 1', Per port HL is set to > DLB2_FIXED_CQ_HL_SIZE (32) and command line parameter > alloc_hl_entries is ignored. > > When 'use_default_hl = 0', Per LDB port HL = 2 * CQ depth and per > port HL is set to 2 * DLB2_FIXED_CQ_HL_SIZE. > > User should calculate needed HL entries based on CQ depths the > application will use and specify it as command line parameter > 'alloc_hl_entries'. This will be used to allocate HL entries. > Hence, alloc_hl_entries = (Sum of all LDB ports CQ depths * 2). > > If alloc_hl_entries is not specified, then Total HL entries for the > vdev = num_ldb_ports * 64. > > Signed-off-by: Abdullah Sevincer <abdullah.sevin...@intel.com>
> } > diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h > index d6828aa482..dc9f98e142 100644 > --- a/drivers/event/dlb2/dlb2_priv.h > +++ b/drivers/event/dlb2/dlb2_priv.h > @@ -52,6 +52,8 @@ > #define DLB2_PRODUCER_COREMASK "producer_coremask" > #define DLB2_DEFAULT_LDB_PORT_ALLOCATION_ARG "default_port_allocation" > #define DLB2_ENABLE_CQ_WEIGHT_ARG "enable_cq_weight" > +#define DLB2_USE_DEFAULT_HL "use_default_hl" > +#define DLB2_ALLOC_HL_ENTRIES "alloc_hl_entries" 1)Update doc/guides/eventdevs/dlb2.rst for new devargs 2)Please release note PMD section for this feature.
