Based on the patch by David Hunt and Armuta Zende:
lib: added support for armv7 architecture
Signed-off-by: Jan Viktorin <viktorin at rehivetech.com>
Signed-off-by: Amruta Zende <amruta.zende at intel.com>
Signed-off-by: David Hunt <david.hunt at intel.com>
---
lib/librte_eal/common/include/arch/arm/rte_cpuflags.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
index 1eadb33..17e13fc 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
@@ -52,10 +52,15 @@ extern "C" {
#define AT_HWCAP2 26
#endif
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
/* software based registers */
enum cpu_register_t {
REG_HWCAP = 0,
REG_HWCAP2,
+ REG_PLATFORM,
};
/**
@@ -89,6 +94,8 @@ enum rte_cpu_flag_t {
RTE_CPUFLAG_SHA1,
RTE_CPUFLAG_SHA2,
RTE_CPUFLAG_CRC32,
+ RTE_CPUFLAG_AARCH32,
+ RTE_CPUFLAG_AARCH64,
/* The last item */
RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
};
@@ -121,6 +128,8 @@ static const struct feature_entry cpu_feature_table[] = {
FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2)
FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3)
FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4)
+ FEAT_DEF(AARCH32, 0x00000001, 0, REG_PLATFORM, 0)
+ FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1)
};
/*
@@ -141,6 +150,12 @@ rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
out[REG_HWCAP] = auxv.a_un.a_val;
else if (auxv.a_type == AT_HWCAP2)
out[REG_HWCAP2] = auxv.a_un.a_val;
+ else if (auxv.a_type == AT_PLATFORM) {
+ if (!strcmp((const char *)auxv.a_un.a_val, "aarch32"))
+ out[REG_PLATFORM] = 0x0001;
+ else if (!strcmp((const char *)auxv.a_un.a_val,
"aarch64"))
+ out[REG_PLATFORM] = 0x0002;
+ }
}
}
--
2.6.1
