On Mon, 1 Apr 2024 18:26:44 -0400 Patrick Robb <pr...@iol.unh.edu> wrote:
> Another idea - maybe multiple timestamps are gathered from different > CPU registers during the same test, and they are misaligned for that > reason. Maybe we can try reducing the cores for each unit test to 1 > and checking whether the issue persists. TSC is expected to be sync'd between cores. But of course packets can arrive out of order on different cores.
