From: Shai Brandes <shaib...@amazon.com>
The dma_rmb() memory barrier guarantees that the device set the
phase bit before continuing to read the rest of the descriptor.
Because the phase bit and the rest of the descriptor are in the same
cache line this ensures coherency of the data from the descriptor.
Signed-off-by: Shai Brandes <shaib...@amazon.com>
Reviewed-by: Amit Bernstein <amitb...@amazon.com>
---
drivers/net/ena/hal/ena_com.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ena/hal/ena_com.c b/drivers/net/ena/hal/ena_com.c
index f9613f7807..053e095585 100644
--- a/drivers/net/ena/hal/ena_com.c
+++ b/drivers/net/ena/hal/ena_com.c
@@ -2412,8 +2412,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev
*ena_dev, void *data)
/* Go over all the events */
while ((READ_ONCE8(aenq_common->flags) &
ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
- /* Make sure the phase bit (ownership) is as expected before
- * reading the rest of the descriptor.
+ /* Make sure the device finished writing the rest of the
descriptor
+ * before reading it.
*/
dma_rmb();
--
2.17.1
