Modified the conditionals in `flow_hw_table_create()` to use bitwise
AND instead of equality checks when assessing
`table_cfg->attr->specialize` bitmask.
This will allow for greater flexibility as the bitmask may encapsulate
multiple flags.
The patch maintains the previous behavior with single flag values,
while providing support for multiple flags.
Fixes: 592d5367b5e4 ("net/mlx5: enable hint in async flow table")
Signed-off-by: Gregory Etelson <getel...@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_hw.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 783ad9e72a..5938d8b90c 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4390,12 +4390,23 @@ flow_hw_table_create(struct rte_eth_dev *dev,
matcher_attr.rule.num_log = rte_log2_u32(nb_flows);
/* Parse hints information. */
if (attr->specialize) {
- if (attr->specialize ==
RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
- matcher_attr.optimize_flow_src =
MLX5DR_MATCHER_FLOW_SRC_WIRE;
- else if (attr->specialize ==
RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
- matcher_attr.optimize_flow_src =
MLX5DR_MATCHER_FLOW_SRC_VPORT;
- else
- DRV_LOG(INFO, "Unsupported hint value %x",
attr->specialize);
+ uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |
+ RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;
+
+ if ((attr->specialize & val) == val) {
+ DRV_LOG(INFO, "Invalid hint value %x",
+ attr->specialize);
+ rte_errno = EINVAL;
+ goto it_error;
+ }
+ if (attr->specialize &
+ RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)
+ matcher_attr.optimize_flow_src =
+ MLX5DR_MATCHER_FLOW_SRC_WIRE;
+ else if (attr->specialize &
+ RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)
+ matcher_attr.optimize_flow_src =
+ MLX5DR_MATCHER_FLOW_SRC_VPORT;
}
/* Build the item template. */
for (i = 0; i < nb_item_templates; i++) {
--
2.39.2
