On Fri, Feb 23, 2024 at 9:35 PM Vamsi Attunuru <vattun...@marvell.com> wrote: > > Adds a devarg option to enable/disable ISM memory accesses > for reading packet count details. This option is disabled > by default, as ISM memory accesses effect throughput of > bigger size packets. > > Signed-off-by: Vamsi Attunuru <vattun...@marvell.com> > --- > doc/guides/nics/octeon_ep.rst | 12 ++++++++ > drivers/net/octeon_ep/cnxk_ep_rx.h | 42 +++++++++++++++++++++----- > drivers/net/octeon_ep/cnxk_ep_tx.c | 42 ++++++++++++++++++++++---- > drivers/net/octeon_ep/cnxk_ep_vf.c | 4 +-- > drivers/net/octeon_ep/otx2_ep_vf.c | 4 +-- > drivers/net/octeon_ep/otx_ep_common.h | 14 +++++++-- > drivers/net/octeon_ep/otx_ep_ethdev.c | 43 +++++++++++++++++++++++++++ > drivers/net/octeon_ep/otx_ep_rxtx.c | 15 ++++++---- > drivers/net/octeon_ep/otx_ep_rxtx.h | 2 ++ > 9 files changed, 153 insertions(+), 25 deletions(-) > > diff --git a/doc/guides/nics/octeon_ep.rst b/doc/guides/nics/octeon_ep.rst > index b5040aeee2..befa0a4097 100644 > --- a/doc/guides/nics/octeon_ep.rst > +++ b/doc/guides/nics/octeon_ep.rst > @@ -11,6 +11,18 @@ and **Cavium OCTEON** families of adapters in SR-IOV > context. > More information can be found at `Marvell Official Website > > <https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-liquidio-III-solutions-brief.pdf>`_. > > +Runtime Config Options > +---------------------- > + > +- ``Rx&Tx ISM memory accesses enable`` (default ``0``) > + > + PMD supports 2 modes for checking Rx & Tx packet count, PMD may read the > packet count directly
2 → two > + from hardware registers or it may read from ISM memory, this may be > selected at runtime > + using ``ism_enable`` ``devargs`` parameter. Furthermore, tell why someone needs to choose one vs. others > + > + For example:: > + > + -a 0002:02:00.0,ism_enable=1 > 1) Update release notes new PMD feature 2) Missing updates to RTE_PMD_REGISTER_PARAM_STRING for devargs
