> On 14. Dec 2023, at 03:24, Zhang, Qi Z <qi.z.zh...@intel.com> wrote:
>> -----Original Message-----
>> From: Simon Ellmann <simon.ellm...@tum.de>
>> Sent: Friday, December 8, 2023 11:44 PM
>> To: Yang, Qiming <qiming.y...@intel.com>; Wu, Wenjun1
>> <wenjun1...@intel.com>
>> Cc: dev@dpdk.org; Simon Ellmann <simon.ellm...@tum.de>
>> Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
>>
>> 32nd bit of the eimc register is reserved according to the datasheet
>>
>> Signed-off-by: Simon Ellmann <simon.ellm...@tum.de>
>> ---
>> drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
>> b/drivers/net/ixgbe/base/ixgbe_type.h
>> index 1094df5891..03b299cd10 100644
>> --- a/drivers/net/ixgbe/base/ixgbe_type.h
>> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
>> @@ -2023,7 +2023,7 @@ enum {
>> #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
>>
>> /* Interrupt clear mask */
>> -#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
>> +#define IXGBE_IRQ_CLEAR_MASK 0x7FFFFFFF
>
> If it is not harmful, I will prefer to keep the base code aligned with kernel
> driver's implementation which is 0xFFFFFFFF currently.
Alright. We fixed this in our driver implementation –
https://github.com/ixy-languages/ixy.rs/issues/29 – and thought we would let
you know.
>>
>> /* Interrupt Vector Allocation Registers */
>> #define IXGBE_IVAR_REG_NUM 25
>> --
>> 2.43.0
>
