On Tue, Nov 28, 2023 at 10:17 PM Srikanth Yalavarthi
<syalavar...@marvell.com> wrote:
>
> From: Anup Prabhu <apra...@marvell.com>
>
> Exclude the hardware and firmware latency of model data
> caching run from xstats calculation.
>
> Fixes: 9cfad6c334f2 ("ml/cnxk: update device and model xstats functions")
>
> Signed-off-by: Anup Prabhu <apra...@marvell.com>
> Acked-by: Srikanth Yalavarthi <syalavar...@marvell.com>
Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-main. Thanks
ml/cnxk: fix xstats calculation
Exclude the hardware and firmware latency of model data
caching run from xstats calculation.
Fixes: 9cfad6c334f2 ("ml/cnxk: update device and model xstats functions")
Cc: sta...@dpdk.org
Signed-off-by: Anup Prabhu <apra...@marvell.com>
Acked-by: Srikanth Yalavarthi <syalavar...@marvell.com>
> ---
> drivers/ml/cnxk/cn10k_ml_ops.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c
> index 7f7e5efceac..53700387335 100644
> --- a/drivers/ml/cnxk/cn10k_ml_ops.c
> +++ b/drivers/ml/cnxk/cn10k_ml_ops.c
> @@ -288,6 +288,7 @@ cn10k_ml_model_xstat_get(struct cnxk_ml_dev *cnxk_mldev,
> struct cnxk_ml_layer *l
> static int
> cn10k_ml_cache_model_data(struct cnxk_ml_dev *cnxk_mldev, struct
> cnxk_ml_layer *layer)
> {
> + struct cn10k_ml_layer_xstats *xstats;
> char str[RTE_MEMZONE_NAMESIZE];
> const struct plt_memzone *mz;
> uint64_t isize = 0;
> @@ -309,6 +310,16 @@ cn10k_ml_cache_model_data(struct cnxk_ml_dev
> *cnxk_mldev, struct cnxk_ml_layer *
> PLT_PTR_ADD(mz->addr, isize), 1);
> plt_memzone_free(mz);
>
> + /* Reset sync xstats. */
> + xstats = layer->glow.sync_xstats;
> + xstats->hw_latency_tot = 0;
> + xstats->hw_latency_min = UINT64_MAX;
> + xstats->hw_latency_max = 0;
> + xstats->fw_latency_tot = 0;
> + xstats->fw_latency_min = UINT64_MAX;
> + xstats->fw_latency_max = 0;
> + xstats->dequeued_count = 0;
> +
> return ret;
> }
>
> --
> 2.42.0
>
