This is a patch to change the value of register 776.20[11:2] for jumbo
mode from 0x1A to 0x1F. This is to enlarge the gap between read and
write pointers in the TX Fifo.
And replace the magic number with a macro by the way.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu at intel.com>
---
drivers/net/e1000/base/e1000_defines.h | 1 +
drivers/net/e1000/base/e1000_ich8lan.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/e1000/base/e1000_defines.h
b/drivers/net/e1000/base/e1000_defines.h
index 71bd2e0..79a88bb 100644
--- a/drivers/net/e1000/base/e1000_defines.h
+++ b/drivers/net/e1000/base/e1000_defines.h
@@ -468,6 +468,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define ETHERNET_FCS_SIZE 4
#define MAX_JUMBO_FRAME_SIZE 0x3F00
+#define E1000_TX_PTR_GAP 0x1F
/* Extended Configuration Control and Size */
#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
diff --git a/drivers/net/e1000/base/e1000_ich8lan.c
b/drivers/net/e1000/base/e1000_ich8lan.c
index f23d810..cc6e033 100644
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -2601,7 +2601,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw, bool enable)
return ret_val;
hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
data &= ~(0x3FF << 2);
- data |= (0x1A << 2);
+ data |= (E1000_TX_PTR_GAP << 2);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
if (ret_val)
return ret_val;
--
1.9.3
