[dpdk-dev] [PATCH v2 28/35] e1000/base: increase timeout of polling bit RSPCIPHY in check_reset_block

[Wenzhuo Lu]

Previously, in check_reset_block RSPCIPHY was polled for 100 ms before 
determining
that the ME veto is set. This needed to be increased to 300 ms.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu at intel.com>
---
 drivers/net/e1000/base/e1000_ich8lan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c 
b/drivers/net/e1000/base/e1000_ich8lan.c
index 7b7c631..70eba71 100644
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -1991,7 +1991,7 @@ STATIC s32 e1000_check_reset_block_ich8lan(struct 
e1000_hw *hw)
                        continue;
                }
                blocked = false;
-       } while (blocked && (i++ < 10));
+       } while (blocked && (i++ < 30));
        return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
 }

-- 
1.9.3