From: Michael Baum <michae...@nvidia.com>
Add limitations for ptype item support in "mlx5.rst" file.
Signed-off-by: Michael Baum <michae...@nvidia.com>
---
doc/guides/nics/features/mlx5.ini | 1 +
doc/guides/nics/mlx5.rst | 15 +++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/doc/guides/nics/features/mlx5.ini
b/doc/guides/nics/features/mlx5.ini
index fc67415c6c..e3927ab4df 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -86,6 +86,7 @@ nsh = Y
nvgre = Y
port_id = Y
port_representor = Y
+ptype = Y
quota = Y
tag = Y
tcp = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 7086f3d1d4..c9e74948cc 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -646,6 +646,21 @@ Limitations
- When using HWS flow engine (``dv_flow_en`` = 2),
only meter mark action is supported.
+- Ptype:
+
+ - Only supports HW steering (``dv_flow_en=2``).
+ - The supported values are:
+ L2: ``RTE_PTYPE_L2_ETHER``, ``RTE_PTYPE_L2_ETHER_VLAN``,
``RTE_PTYPE_L2_ETHER_QINQ``
+ L3: ``RTE_PTYPE_L3_IPV4``, ``RTE_PTYPE_L3_IPV6``
+ L4: ``RTE_PTYPE_L4_TCP``, ``RTE_PTYPE_L4_UDP``, ``RTE_PTYPE_L4_ICMP``
+ and their ``RTE_PTYPE_INNER_XXX`` counterparts as well as
``RTE_PTYPE_TUNNEL_ESP``.
+ Any other values are not supported. Using them as a value will cause
unexpected behavior.
+ - Matching on both outer and inner IP fragmented is supported using
``RTE_PTYPE_L4_FRAG`` and
+ ``RTE_PTYPE_INNER_L4_FRAG`` values. They are not part of L4 types, so they
should be provided
+ explicitly as a mask value during pattern template creation. Providing
``RTE_PTYPE_L4_MASK``
+ during pattern template creation and ``RTE_PTYPE_L4_FRAG`` during flow
rule creation
+ will cause unexpected behavior.
+
- Integrity:
- Integrity offload is enabled starting from **ConnectX-6 Dx**.
--
2.18.2
